From c22e4baa41f969d99d1598694ce696ac37d32929 Mon Sep 17 00:00:00 2001 From: Ed_ Date: Fri, 10 Jul 2026 19:51:41 -0400 Subject: [PATCH] minor adjustmnets to some headers (doing a review pass) --- code/duffle/gen/duffle.macs.h | 24 ++++++++++++------------ code/duffle/gp.h | 34 +++++++++++----------------------- code/duffle/lottes_tape.h | 32 +++++++++++++++----------------- 3 files changed, 38 insertions(+), 52 deletions(-) diff --git a/code/duffle/gen/duffle.macs.h b/code/duffle/gen/duffle.macs.h index 283f0e9..13dad8d 100644 --- a/code/duffle/gen/duffle.macs.h +++ b/code/duffle/gen/duffle.macs.h @@ -51,12 +51,12 @@ WORD_COUNT(mac_gte_load_tri_verts, 18) shift_lleft( R_T1, R_T1, S_(U4)/2) /* T1 = otz * S_(U4) (otz arg is implicit R_T1) */ \ , add_u_self( R_T1, R_OtBase) /* T1 = & OrderingTable[OTZ] */ \ , load_word( R_AT, R_T1, O_(PolyTag,bf_addr_len)) /* AT = old_ot_head */ \ -, load_upper_i(R_V0, (S_(Poly_F3)/S_(U4) - S_(PolyTag)/S_(U4)) << polytag_len_bits) /* V0 = (5 - 1) << 24 = 4 << 24 */ \ -, mask_upper( R_AT, R_AT, S_(polytag_len_bits)) /* Strip upper 8 bits (length from prev cell) → keep only low 24 */ \ +, load_upper_i(R_V0, (S_(Poly_F3)/S_(U4) - S_(PolyTag)/S_(U4)) << PolyTag_len_bits) /* V0 = (5 - 1) << 24 = 4 << 24 */ \ +, mask_upper( R_AT, R_AT, S_(PolyTag_len_bits)) /* Strip upper 8 bits (length from prev cell) → keep only low 24 */ \ , or_u( R_AT, R_AT, R_V0) /* Merge length */ \ , store_word( R_AT, R_PrimCursor, O_(PolyTag,bf_addr_len)) /* prim->tag = packed(prim_length, old_addr) */ \ -, shift_lleft( R_AT, R_PrimCursor, S_(polytag_len_bits)) /* AT = (prim_length << 24) | old_addr */ \ -, shift_lright(R_AT, R_AT, S_(polytag_len_bits)) \ +, shift_lleft( R_AT, R_PrimCursor, S_(PolyTag_len_bits)) /* AT = (prim_length << 24) | old_addr */ \ +, shift_lright(R_AT, R_AT, S_(PolyTag_len_bits)) \ , store_word( R_AT, R_T1, O_(PolyTag,bf_addr_len)) /* OrderingTable[OTZ] = PrimCursor */ WORD_COUNT(mac_insert_ot_tag_f3, 11) @@ -66,17 +66,17 @@ WORD_COUNT(mac_insert_ot_tag_f3, 11) shift_lleft( R_T1, R_T1, S_(U4)/2) /* T1 = otz * S_(U4) (otz arg is implicit R_T1) */ \ , add_u_self( R_T1, R_OtBase) /* T1 = & OrderingTable[OTZ] */ \ , load_word( R_AT, R_T1, O_(PolyTag,bf_addr_len)) /* AT = old_ot_head */ \ -, load_upper_i(R_V0, (S_(Poly_G4)/S_(U4) - S_(PolyTag)/S_(U4)) << polytag_len_bits) /* V0 = (9 - 1) << 24 = 8 << 24 */ \ -, mask_upper( R_AT, R_AT, S_(polytag_len_bits)) /* Strip upper 8 bits (length from prev cell) → keep only low 24 */ \ +, load_upper_i(R_V0, (S_(Poly_G4)/S_(U4) - S_(PolyTag)/S_(U4)) << PolyTag_len_bits) /* V0 = (9 - 1) << 24 = 8 << 24 */ \ +, mask_upper( R_AT, R_AT, S_(PolyTag_len_bits)) /* Strip upper 8 bits (length from prev cell) → keep only low 24 */ \ , or_u( R_AT, R_AT, R_V0) /* Merge length */ \ , store_word( R_AT, R_PrimCursor, O_(PolyTag,bf_addr_len)) /* prim->tag = packed(prim_length, old_addr) */ \ -, shift_lleft( R_AT, R_PrimCursor, S_(polytag_len_bits)) /* AT = (prim_length << 24) | old_addr */ \ -, shift_lright(R_AT, R_AT, S_(polytag_len_bits)) \ +, shift_lleft( R_AT, R_PrimCursor, S_(PolyTag_len_bits)) /* AT = (prim_length << 24) | old_addr */ \ +, shift_lright(R_AT, R_AT, S_(PolyTag_len_bits)) \ , store_word( R_AT, R_T1, O_(PolyTag,bf_addr_len)) /* OrderingTable[OTZ] = PrimCursor */ WORD_COUNT(mac_insert_ot_tag_g4, 11) -#define mac_pack_color_word(off, code, r, g, b) \ - load_upper_i(R_AT, (code) << 8 | (b)) \ +#define mac_pack_color_word(off, cmd, r, g, b) \ + load_upper_i(R_AT, (cmd) << 8 | (b)) \ , or_i_self( R_AT, ((g) << 8) | (r)) \ , store_word( R_AT, R_PrimCursor, (off)) WORD_COUNT(mac_pack_color_word, 3) @@ -102,8 +102,8 @@ WORD_COUNT(mac_format_g4_color, 12) /* Words: 3; Stores the 3 transformed (V2_S2 screen) vertices of the * G4 triangle portion to p0/p1/p2. - * PIPELINE: post-RTPT, pre-RTPS (SXY0=v0.screen, SXY1=v1.screen, - * SXY2=v2.screen). MUST be called BEFORE V3-RTPS, otherwise SXY0/1/2 + * PIPELINE: post-RTPT, pre-RTPS (SXY0=v0.screen, SXY1=v1.screen, SXY2=v2.screen). + * MUST be called BEFORE V3-RTPS, otherwise SXY0/1/2 * get overwritten with v3 (RTPS writes only to SXY2, but to keep the * three registers aligned with v0/v1/v2 you must store before RTPS). * The macro name declares the pipeline position; check #6 (GTE state- diff --git a/code/duffle/gp.h b/code/duffle/gp.h index a1b4037..473d41f 100644 --- a/code/duffle/gp.h +++ b/code/duffle/gp.h @@ -51,10 +51,7 @@ * tape-side macros that pin a register to hold the IO base and access * ports via offsets — `lui $reg, 0x1F80` (1 word) then `sw $data, * GPIO_PORT*_OFFSET($reg)` (1 word). Mirrors the `IO_BASE_ADDR equ - * 0x1F80` + `gpio_port0 equ 0x1810` pattern from graphics_hello/gp.s. - * - * See lottes_tape.h `R_GpIoBase` + `mac_gp0_send_imm` for the - * wave-context form that composes these primitives. */ + * 0x1F80` + `gpio_port0 equ 0x1810` pattern from graphics_hello/gp.s. */ enum { IO_BASE_ADDR = 0x1F800000, /* full 32-bit I/O region base */ IO_BASE_ADDR_HI16 = 0x1F80, /* fits in a single `lui $reg, 0x1F80` */ @@ -120,8 +117,7 @@ enum { gp0_cmd_tile_8 = 0x68, gp0_cmd_tile_16 = 0x70, - /* State setters (not drawing primitives; set render context). - * Per PSX-SPX graphicsprocessingunitgpu.md §"GP0 Other Commands". */ + /* State setters (not drawing primitives; set render context). */ gp0_cmd_DrawModeSetting = 0xE1, /* TPage / draw-mode (semi-trans, dither, etc.) */ gp0_cmd_SetTextureWindow = 0xE2, gp0_cmd_SetDrawArea_TopLeft = 0xE3, @@ -130,9 +126,7 @@ enum { gp0_cmd_SetMaskBit = 0xE6, /* bitfield shifts / widths / masks ---- - * - * Generic GP0/GP1 command byte (upper 8 bits of every word sent - * to either port). Used by `enc_gp0_cmd(cmd)` and friends below. */ + * Generic GP0/GP1 command byte (upper 8 bits of every word sent to either port). */ gp0_cmd_shift = 24, gp0_cmd_width = 8, gp0_cmd_mask = 0xFF, @@ -294,12 +288,6 @@ enum { * Common command words for boot-time GPU init and standard * display configurations. Each one is a pure compile-time integer * constant ready to drop into a `.word` directive. - * - * These are the equivalents of the `gp_HorizontalDisplayRange_3168_608`, - * `gp_VerticalDisplayRange_264_24`, `gp_DisplayMode_320x240_15bit_NTSC`, - * `gp_SetDrawMode_DrawAllowed`, `gp_DMA_*` `.equ`s from the pre-rewrite - * gp.h / graphics_hello/gp.s, rebuilt using the layer-cake encoders so - * no magic numbers appear in any body. * ============================================================================ */ /* ---- Display enable (1-bit payload on DisplayEnable cmd) ---- */ @@ -391,8 +379,8 @@ typedef Struct_(RGB8) { B1 r; B1 g; B1 b; }; /* ---------- PolyTag (the OT-link header; 1 word) ---------- */ enum { - polytag_len_bits = 8, - polytag_addr_bits = 24, + PolyTag_len_bits = 8, + PolyTag_addr_bits = 24, }; typedef Struct_(PolyTag) { union { @@ -468,7 +456,7 @@ typedef Struct_(Poly_FT3) { V2_S2 p2; U1 u2; U1 v2; }; -/* ---------- Poly_FT4 (Flat Textured Quad; placeholder layout) ---------- */ +/* ---------- Poly_FT4 (Flat Textured Quad) ---------- */ typedef Struct_(Poly_FT4) { U4 tag; RGB8 color; @@ -481,7 +469,7 @@ typedef Struct_(Poly_FT4) { V2_S2 p3; U1 u3; U1 v3; }; -/* ---------- Poly_GT3 (Gouraud Textured Triangle; placeholder layout) ---------- */ +/* ---------- Poly_GT3 (Gouraud Textured Triangle) ---------- */ typedef Struct_(Poly_GT3) { U4 tag; RGB8 c0; B1 code; V2_S2 p0; RGB8 c1; B1 pad1; @@ -494,7 +482,7 @@ typedef Struct_(Poly_GT3) { V2_S2 tp2; U1 u2; U1 v2; }; -/* ---------- Poly_GT4 (Gouraud Textured Quad; placeholder layout) ---------- */ +/* ---------- Poly_GT4 (Gouraud Textured Quad) ---------- */ typedef Struct_(Poly_GT4) { U4 tag; RGB8 c0; B1 code; V2_S2 p0; RGB8 c1; B1 pad1; @@ -509,7 +497,7 @@ typedef Struct_(Poly_GT4) { V2_S2 tp3; U1 u3; U1 v3; }; -/* ---------- Primitive setters (C-level, no emitted words) ---------- +/* ---------- Primitive setters (C-level) ---------- * DSL cast convention: every cast via C_(), every pointer via R_/V_. */ #define set_poly_f3(p) set_len(p, 4), C_(Poly_F3_R, p)->code = gp0_cmd_poly_f3 #define set_poly_ft3(p) set_len(p, 7), C_(Poly_FT3_R,p)->code = gp0_cmd_poly_ft3 @@ -647,7 +635,7 @@ enum { * * Future?: add `tim_load_to_vram(tim_ptr, vram_addr)` that * emits the necessary GP0 commands. Stoppped for now at the - * struct + enum level for this track. + * struct + enum level. * ============================================================================ */ enum { tim_file_id_magic = 0x10, @@ -660,7 +648,7 @@ enum { }; typedef Struct_(TIM_Header) { - U4 file_id; /* always 0x10 = "TIM" magic */ + U4 file_id; /* always 0x10 = "TIM" magic */ U4 version; /* ignored; always 0 */ U4 flags; /* bits 0..2 = type, bit 3 = has_clut */ }; diff --git a/code/duffle/lottes_tape.h b/code/duffle/lottes_tape.h index aff6093..f862a73 100644 --- a/code/duffle/lottes_tape.h +++ b/code/duffle/lottes_tape.h @@ -134,12 +134,12 @@ MipsAtomComp_(ac_insert_ot_tag_f3) { shift_lleft( R_T1, R_T1, S_(U4)/2), // T1 = otz * S_(U4) (otz arg is implicit R_T1) add_u_self( R_T1, R_OtBase), // T1 = & OrderingTable[OTZ] load_word( R_AT, R_T1, O_(PolyTag,bf_addr_len)), // AT = old_ot_head - load_upper_i(R_V0, (S_(Poly_F3)/S_(U4) - S_(PolyTag)/S_(U4)) << polytag_len_bits), // V0 = (5 - 1) << 24 = 4 << 24 - mask_upper( R_AT, R_AT, S_(polytag_len_bits)), // Strip upper 8 bits (length from prev cell) → keep only low 24 + load_upper_i(R_V0, (S_(Poly_F3)/S_(U4) - S_(PolyTag)/S_(U4)) << PolyTag_len_bits), // V0 = (5 - 1) << 24 = 4 << 24 + mask_upper( R_AT, R_AT, S_(PolyTag_len_bits)), // Strip upper 8 bits (length from prev cell) → keep only low 24 or_u( R_AT, R_AT, R_V0), // Merge length store_word( R_AT, R_PrimCursor, O_(PolyTag,bf_addr_len)), // prim->tag = packed(prim_length, old_addr) - shift_lleft( R_AT, R_PrimCursor, S_(polytag_len_bits)), // AT = (prim_length << 24) | old_addr - shift_lright(R_AT, R_AT, S_(polytag_len_bits)), + shift_lleft( R_AT, R_PrimCursor, S_(PolyTag_len_bits)), // AT = (prim_length << 24) | old_addr + shift_lright(R_AT, R_AT, S_(PolyTag_len_bits)), store_word( R_AT, R_T1, O_(PolyTag,bf_addr_len)), // OrderingTable[OTZ] = PrimCursor }; @@ -149,22 +149,20 @@ MipsAtomComp_(ac_insert_ot_tag_g4) { shift_lleft( R_T1, R_T1, S_(U4)/2), // T1 = otz * S_(U4) (otz arg is implicit R_T1) add_u_self( R_T1, R_OtBase), // T1 = & OrderingTable[OTZ] load_word( R_AT, R_T1, O_(PolyTag,bf_addr_len)), // AT = old_ot_head - load_upper_i(R_V0, (S_(Poly_G4)/S_(U4) - S_(PolyTag)/S_(U4)) << polytag_len_bits), // V0 = (9 - 1) << 24 = 8 << 24 - mask_upper( R_AT, R_AT, S_(polytag_len_bits)), // Strip upper 8 bits (length from prev cell) → keep only low 24 + load_upper_i(R_V0, (S_(Poly_G4)/S_(U4) - S_(PolyTag)/S_(U4)) << PolyTag_len_bits), // V0 = (9 - 1) << 24 = 8 << 24 + mask_upper( R_AT, R_AT, S_(PolyTag_len_bits)), // Strip upper 8 bits (length from prev cell) → keep only low 24 or_u( R_AT, R_AT, R_V0), // Merge length store_word( R_AT, R_PrimCursor, O_(PolyTag,bf_addr_len)), // prim->tag = packed(prim_length, old_addr) - shift_lleft( R_AT, R_PrimCursor, S_(polytag_len_bits)), // AT = (prim_length << 24) | old_addr - shift_lright(R_AT, R_AT, S_(polytag_len_bits)), + shift_lleft( R_AT, R_PrimCursor, S_(PolyTag_len_bits)), // AT = (prim_length << 24) | old_addr + shift_lright(R_AT, R_AT, S_(PolyTag_len_bits)), store_word( R_AT, R_T1, O_(PolyTag,bf_addr_len)), // OrderingTable[OTZ] = PrimCursor }; /* Words: 3; Emits one (cmd|color) word to R_PrimCursor at the given - * byte offset. Internal helper used by the *_format_*_color macros. - * Args: off = U4 byte offset, code = GP0 cmd byte (0 for c1/c2/c3 of - * a Poly_G4), r/g/b = 8-bit RGB byte values. */ -FI_ MipsAtom ac_pack_color_word(U4 off, U4 code, U1 r, U1 g, U1 b) + * byte offset. Internal helper used by the *_format_*_color macros. */ +FI_ MipsAtom ac_pack_color_word(U4 off, U4 cmd, U1 r, U1 g, U1 b) MipsAtomComp_Proc_(ac_pack_color_word, { - load_upper_i(R_AT, (code) << 8 | (b)), + load_upper_i(R_AT, (cmd) << 8 | (b)), or_i_self( R_AT, ((g) << 8) | (r)), store_word( R_AT, R_PrimCursor, (off)), }) @@ -199,8 +197,8 @@ MipsAtomComp_Proc_(ac_format_g4_color, { /* Words: 3; Stores the 3 transformed (V2_S2 screen) vertices of the * G4 triangle portion to p0/p1/p2. - * PIPELINE: post-RTPT, pre-RTPS (SXY0=v0.screen, SXY1=v1.screen, - * SXY2=v2.screen). MUST be called BEFORE V3-RTPS, otherwise SXY0/1/2 + * PIPELINE: post-RTPT, pre-RTPS (SXY0=v0.screen, SXY1=v1.screen, SXY2=v2.screen). + * MUST be called BEFORE V3-RTPS, otherwise SXY0/1/2 * get overwritten with v3 (RTPS writes only to SXY2, but to keep the * three registers aligned with v0/v1/v2 you must store before RTPS). * The macro name declares the pipeline position; check #6 (GTE state- @@ -321,9 +319,9 @@ internal MipsAtom_(diag_color) { add_u_self( R_T1, R_T6), load_word( R_AT, R_T1, 0), - load_upper_i(R_V0, (S_(Poly_F3)/S_(U4) - S_(PolyTag)/S_(U4)) << polytag_len_bits), + load_upper_i(R_V0, (S_(Poly_F3)/S_(U4) - S_(PolyTag)/S_(U4)) << PolyTag_len_bits), store_word( R_AT, R_T7, 0), - shift_lleft(R_AT, R_T7, S_(polytag_len_bits)), shift_lright(R_AT, R_AT, S_(polytag_len_bits)), + shift_lleft(R_AT, R_T7, S_(PolyTag_len_bits)), shift_lright(R_AT, R_AT, S_(PolyTag_len_bits)), or_u_self( R_AT, R_V0), store_word( R_AT, R_T1, 0),