mirror of
https://github.com/Ed94/pikuma_ps1.git
synced 2026-08-04 14:48:48 +00:00
redundant nop reduction
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@@ -115,11 +115,8 @@ WORD_COUNT(mac_format_g4_color, 12)
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/* Words: 3; Stores the 3 transformed (V2_S2 screen) vertices of the
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* G4 triangle portion to p0/p1/p2.
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* PIPELINE: post-RTPT, pre-RTPS (SXY0=v0.screen, SXY1=v1.screen, SXY2=v2.screen).
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* MUST be called BEFORE V3-RTPS, otherwise SXY0/1/2
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* get overwritten with v3 (RTPS writes only to SXY2, but to keep the
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* three registers aligned with v0/v1/v2 you must store before RTPS).
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* The macro name declares the pipeline position; check #6 (GTE state-
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* machine validation) verifies the call site matches the declaration. */
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* MUST be called BEFORE V3-RTPS, otherwise SXY0/1/2 get overwritten with v3
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* (RTPS writes only to SXY2, but to keep the three registers aligned with v0/v1/v2 you must store before RTPS). */
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#define mac_gte_store_g4_p012_post_rtpt_pre_rtps(...) \
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gte_sw(C2_SXY0, R_PrimCursor, O_(Poly_G4,p0)) \
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, gte_sw(C2_SXY1, R_PrimCursor, O_(Poly_G4,p1)) \
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@@ -128,10 +125,8 @@ WORD_COUNT(mac_gte_store_g4_p012_post_rtpt_pre_rtps, 3)
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/* atom_dbg_skip */
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/* Words: 1; Stores the V3 screen coord to the G4's p3 slot.
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* PIPELINE: post-RTPS (SXY2 holds v3.screen because RTPS writes its
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* single-vertex result to SXY2; SXY0 still holds v0.screen from the
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* earlier RTPT — DO NOT read SXY0 here, that's the bug this name
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* prevents).
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* PIPELINE: post-RTPS (SXY2 holds v3.screen because RTPS writes its single-vertex result to SXY2;
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* SXY0 still holds v0.screen from the earlier RTPT.
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*/
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#define mac_gte_store_g4_p3_post_rtps(...) \
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gte_sw(C2_SXY2, R_PrimCursor, O_(Poly_G4,p3))
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@@ -193,11 +193,8 @@ MipsAtomComp_Proc_(ac_format_g4_color, {
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/* Words: 3; Stores the 3 transformed (V2_S2 screen) vertices of the
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* G4 triangle portion to p0/p1/p2.
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* PIPELINE: post-RTPT, pre-RTPS (SXY0=v0.screen, SXY1=v1.screen, SXY2=v2.screen).
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* MUST be called BEFORE V3-RTPS, otherwise SXY0/1/2
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* get overwritten with v3 (RTPS writes only to SXY2, but to keep the
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* three registers aligned with v0/v1/v2 you must store before RTPS).
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* The macro name declares the pipeline position; check #6 (GTE state-
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* machine validation) verifies the call site matches the declaration. */
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* MUST be called BEFORE V3-RTPS, otherwise SXY0/1/2 get overwritten with v3
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* (RTPS writes only to SXY2, but to keep the three registers aligned with v0/v1/v2 you must store before RTPS). */
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atom_dbg_skip MipsAtomComp_(ac_gte_store_g4_p012_post_rtpt_pre_rtps) {
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gte_sw(C2_SXY0, R_PrimCursor, O_(Poly_G4,p0)),
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gte_sw(C2_SXY1, R_PrimCursor, O_(Poly_G4,p1)),
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@@ -205,10 +202,8 @@ atom_dbg_skip MipsAtomComp_(ac_gte_store_g4_p012_post_rtpt_pre_rtps) {
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};
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/* Words: 1; Stores the V3 screen coord to the G4's p3 slot.
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* PIPELINE: post-RTPS (SXY2 holds v3.screen because RTPS writes its
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* single-vertex result to SXY2; SXY0 still holds v0.screen from the
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* earlier RTPT — DO NOT read SXY0 here, that's the bug this name
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* prevents).
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* PIPELINE: post-RTPS (SXY2 holds v3.screen because RTPS writes its single-vertex result to SXY2;
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* SXY0 still holds v0.screen from the earlier RTPT.
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*/
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atom_dbg_skip MipsAtomComp_(ac_gte_store_g4_p3_post_rtps) { gte_sw(C2_SXY2, R_PrimCursor, O_(Poly_G4,p3)) };
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