mirror of
https://github.com/Ed94/pikuma_ps1.git
synced 2026-08-25 02:20:33 +00:00
Collapse of atom 6-9 into a single atom (finaly). Generalized cross product atom proc and atom component. Still working on normalize_v3s4.
This commit is contained in:
+57
-36
@@ -30,10 +30,26 @@ FI_ Slice_MipsCode ac_gte_ld_ir123_v3s4(AtomBuilder_R ab, Reg_(V3_S4) v) MipsAto
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gte_mv_to_data_r(v.z, C2_IR3),
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})
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/* ─── GTE OP cross product (a × b → a) ───
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* Sets up RT diagonal from a.xyz, IR1/2/3 from b.xyz, fires OP,
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* reads MAC1/2/3, shifts right 12 (S12.20 → S12.0 OuterProduct12), writes back to a.xyz.
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* Composes the three sub-primitives (RT-load, IR-load, OP, MAC-read, shift)
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* into one component for use by atoms that need the cross product inline.
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*
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* Output gpr (a) aliases source-A gpr; MAC read clobbers source-A's load targets,
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* but by that point the RT load is complete and source A is dead.
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* Pipeline: clobbers IR1..3, MAC1..3, RT11..33.
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*
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* The CPU→COP2 transfer chains (3 ctc2, 3 mtc2) require a 2-slot retirement gap,
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* and the MFC2→GPR chain (3 mfc2) requires a 1-slot retirement gap, before the GPR can be read.
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* The hazard nops are inlined below — same convention as ac_gte_gpf_scale — so any atom body inlining this component inherits them.
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*
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* Words: 18 (3 ctc2 + 2 nop + 3 mtc2 + 2 nop + 1 op + 3 mfc2 + 1 nop + 3 sra).
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*/
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FI_ Slice_MipsCode ac_gte_op_cross_v3s4(AtomBuilder_R ab, Reg_(V3_S4) a, Reg_(V3_S4) b) atom_dbg_skip MipsAtomComp_Proc_(ab, {
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mac_gte_mv_to_cr_diag_v3s4(a), GteDelay_ /* RT diagonal: D1 = a.x, D2 = a.y, D3 = a.z */
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mac_gte_ld_ir123_v3s4(b), GteDelay_ /* IR: second operand (b.xyz) */
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gte_cmdw_cross, /* OP: MAC1/2/3 = a × b (S12.20) */
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gte_cmdw_cross, /* OP: MAC1/2/3 = a × b (S12.20) */
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mac_gte_mv_from_mac123_v3s4(a), GteDelay_ /* Read MAC1/2/3 → a.xyz (overwrites source-A's load targets) */
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mac_shift_aright_v3s4_self(a, 12), /* Right-shift MAC by 12 (S12.20 → S12.0 OuterProduct12) */
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})
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@@ -226,7 +242,8 @@ FI_ Slice_MipsCode ac_gte_mv_from_mac123_v3s4(AtomBuilder_R ab, Reg_(V3_S4) v) M
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* and the load upper_halves of the table bracket the input range.
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* The later 64 entries (octaves 2-3) are the `srav` branch when the magnitude's top bit is well above bit 24.
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*
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* 192-entry table is reproduced verbatim from libgte (verified against libpsn00b/psxgte/vector.s:100-123 — 24 rows × 8 halfwords, last entry 0x0804). */
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* Reproduced verbatim from libgte (verified against libpsn00b/psxgte/vector.s:100-123 — 24 rows × 8 halfwords, last entry 0x0804).
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* */
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internal S2 const gte_normalize_sqr_tbl[192] align_(2) = {
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0x1000, 0x0fe0, 0x0fc1, 0x0fa3, 0x0f85, 0x0f68, 0x0f4c, 0x0f30,
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0x0f15, 0x0efb, 0x0ee1, 0x0ec7, 0x0eae, 0x0e96, 0x0e7e, 0x0e66,
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@@ -254,39 +271,40 @@ internal S2 const gte_normalize_sqr_tbl[192] align_(2) = {
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0x0820, 0x081c, 0x0818, 0x0814, 0x0810, 0x080c, 0x0808, 0x0804,
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};
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typedef Struct_(Binds_build_normalize_v3s4) {
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U4 scratch;
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U2 src_offset;
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U2 dst_offset;
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typedef Struct_(Binds_NormalizeV3S4) {
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U2 src_offset; /* offset of src V3_S4 within the BIOS scratchpad */
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U2 dst_offset; /* offset of dst V3_S4 within the BIOS scratchpad */
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};
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typedef Struct_(RegUse_build_normalize_v3s4) {
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Reg scratch;
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Reg scratch; /* scratchpad base; loaded via load_word_imm below. */
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Reg src_ptr;
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Reg dst_ptr;
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Reg recip_est; // |v|² sum + shift-input + sqrtbl[index]
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Reg recip_est; /* |v|² sum + shift-input + sqrtbl[index] */
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Reg norm; Reg shift;
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Reg src_x;
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union { Reg mac1_scratch; } t3;
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union { Reg mac1_scratch, dst_offset; } t3;
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union { Reg mac2_scratch; } t4;
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union { Reg btarget, shift_count, lookup_addr, src_z; } t5;
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union { Reg btarget, shift_count, lookup_addr, src_z, src_offset; } t5;
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};
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/* ─── Full normalize (all 4 stages inline) ───
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* Generic 4-stage GTE normalize (SQR → sum+LZCR → align+sqrtbl → GPF+srav).
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*
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* Direct port of PSYQ libgte msc02.rel.text VectorNormal disassembly (0x800160a0..0x8001615c).
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* Words: ~59 (matches libgte 0x800160a0..0x8001615c at +/- 0-2 words for BD-slot reshuffling).
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* Sqrtbl: hardcoded to 0x800185B4 (libgte msc02.rel.data). Note: swapped to local.
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* Pipeline: clobbers IR0..3, MAC1..3, LZCS, LZCR.
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*/
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internal MipsAtom* build_normalize_v3s4(AtomArena_R aa, U2 src_offset, U2 dst_offset, RegUse_build_normalize_v3s4 r)
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* Generic 4-stage GTE normalize (SQR → sum+LZCR → align+sqrtbl → GPF+srav). */
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internal MipsAtom* build_normalize_v3s4(AtomArena_R aa, RegUse_build_normalize_v3s4 r)
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MipsAtom_Proc_(aa, {
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// load_word(r.scratch, R_TapePtr, O_(Binds_build_normalize_v3s4,scratch)),
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// add_ui_self(R_TapePtr, S_(Binds_build_normalize_v3s4)),
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add_si(r.src_ptr, r.scratch, src_offset), /* r_src_ptr = &src */
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/* Load scratch base via immediate (always Scratchpad_Loc = 0x1F800000 — the BIOS
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* scratchpad, aliased by every consumer's ResolveLookAtScratch struct). */
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mac_load_word_imm(r.scratch, Scratchpad_Loc),
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/* Tape pop: src_offset, dst_offset = 4 bytes (packed into 1 U4: low16=src, high16=dst).
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* Loads back-to-back fill each other's load-delay slots; the subsequent add_u
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* (2 cycles after the matching load) sees a valid value. */
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load_half(r.t5.src_offset, R_TapePtr, O_(Binds_NormalizeV3S4, src_offset)),
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load_half(r.t3.dst_offset, R_TapePtr, O_(Binds_NormalizeV3S4, dst_offset)),
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LdSlot_ add_u(r.src_ptr, r.scratch, r.t5.src_offset),
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LdSlot_ add_u(r.dst_ptr, r.scratch, r.t3.dst_offset),
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LdSlot_ add_ui_self(R_TapePtr, S_(Binds_NormalizeV3S4)),
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/* Load src.x/y/z from r_src_ptr (caller-determined address) into r_tmp/r_recip_est/r_branch_tmp.
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* r.rt1_src_x holds src.x throughout stages 1-2 — r_mac2_scratch is clobbered to MAC2 in stage 1.5 (line below). */
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* r.rt1_src_x holds src.x throughout stages 1-2 — r_mac2_scratch is clobbered to MAC2 in stage 1.5 (line below).
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* t5.src_offset/dst_offset are dead by here; t5 is reused for src.z in the mac_load_word_v3 below. */
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mac_load_word_v3(r.src_x, r.recip_est, r.t5.src_z, r.src_ptr, 0),
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/* Stage 1: mtc2 src → IR1/2/3, SQR fires. */
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@@ -326,12 +344,12 @@ MipsAtom_Proc_(aa, {
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/* Stage 4: GPF + srav finalize (r_shift = shift count, r_norm = 1/|v|). */
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LdSlot_ mac_gte_general_purpose_interopolation(
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r.norm,
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r.norm,
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r.src_x, /* IR1 = src.x (preserved in r_tmp — r_mac2_scratch was clobbered to MAC2 in stage 1.5) */
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r.recip_est,
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r.recip_est,
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r.t5.src_z, /* IR3 = src.z (reloaded) */
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r.t4.mac2_scratch, r.recip_est, r.t5.src_z,
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GteDelay_ add_si(r.dst_ptr, r.scratch, dst_offset), // pre-laoding destination to register here.
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GteDelay_ nop,
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GteDelay_ nop
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),
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/* sra by r_shift = (31-LZCR)/2 (saved before sqrtbl lookup) */
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@@ -342,25 +360,28 @@ MipsAtom_Proc_(aa, {
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mac_yield()
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})
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/* ─── GTE OP cross product (a × b → out) ───
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* Generalized V3_S4 cross product via GTE OP (OuterProduct12 libpsyx convention).
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* The >> 12 shift converts S12.20 → S12.0 OuterProduct12. */
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typedef Struct_(Binds_gte_cross_v3s4) { V3_S4* src_a; V3_S4* src_b; V3_S4* out; };
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typedef Struct_(RegUse_gte_cross_v3s4) {
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Reg_(V3_S4) a;
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Reg_(V3_S4) b;
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union { Reg t0, out; };
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union { Reg t1, src_a, rt11; };
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union { Reg t2, src_b, rt22; };
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union { Reg out, t0; } x;
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union { Reg src_a, t1, rt11; } y;
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union { Reg src_b, t2, rt22; } z;
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};
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internal MipsAtom* gte_cross_v3s4(AtomArena_R aa, RegUse_gte_cross_v3s4 r)
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atom_info(atom_bind(Binds_gte_cross_v3s4)) MipsAtom_Proc_(aa, {
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load_word(r.src_a, R_TapePtr, O_(Binds_gte_cross_v3s4,src_a)),
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load_word(r.src_b, R_TapePtr, O_(Binds_gte_cross_v3s4,src_b)),
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load_word(r.out, R_TapePtr, O_(Binds_gte_cross_v3s4,out)),
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load_word(r.y.src_a, R_TapePtr, O_(Binds_gte_cross_v3s4,src_a)),
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load_word(r.z.src_b, R_TapePtr, O_(Binds_gte_cross_v3s4,src_b)),
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load_word(r.x.out, R_TapePtr, O_(Binds_gte_cross_v3s4,out)),
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LdSlot_ add_ui_self(R_TapePtr, S_(Binds_gte_cross_v3s4)),
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mac_load_v3s4(r.a, r.src_a, 0), LdSlot_
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mac_load_v3s4(r.b, r.src_b, 0), LdSlot_
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mac_gte_op_cross_v3s4(r.a, r.b), /* RT diagonal + IR + OP + MAC read + shift (one component call). */
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mac_store_v3s4(r.a, r.out, 0),
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mac_load_v3s4(r.a, r.y.src_a, 0), LdSlot_
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mac_load_v3s4(r.b, r.z.src_b, 0), LdSlot_
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mac_gte_op_cross_v3s4(r.a, r.b), /* RT diagonal + IR + OP + MAC read + shift */
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mac_store_v3s4(r.a, r.x.out, 0),
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mac_yield()
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})
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