oops

code/duffle/gte.atom.c

@@ -277,8 +277,8 @@ typedef Struct_(RegUse_build_normalize_v3s4) {
 	union { Reg r1, dst_ptr; };
 	union { Reg r2, dst_offset, mac1, v_sqr_aligned; };
 	union { Reg r3, src_offset, btarget, shift_count, sqrtbl_index; };
-	union { Reg r4, mac3, v_sqr_sum, half_shift_tmp, inv_len; };
+	union { Reg r4, mac3, v_sqr_sum, scale_exp, inv_len; };
-	union { Reg r5, lzcr, half_shift; };
+	union { Reg r5, lzcr, srav_shift; };
 };
 /* ─── Full normalize (all 4 stages inline) ───
  * Generic 4-stage GTE normalize (SQR → sum+LZCR → align+sqrtbl → GPF+srav). */
@@ -313,7 +313,7 @@ MipsAtom_Proc_(aa, {
 			sub_s(r.shift_count, r.shift_count, r.lzcr),
 			shift_aright_var(r.v_sqr_aligned, r.v_sqr_aligned, r.shift_count),
 	atom_label(aligned_done)
-		or_u(r.half_shift, r.half_shift_tmp, 0),
+		or_u(r.srav_shift, r.scale_exp, 0),
 		add_si(     r.v_sqr_aligned, r.v_sqr_aligned, -64),
 		shift_lleft(r.v_sqr_aligned, r.v_sqr_aligned, 1),
 		mac_load_word_imm(r.sqrtbl_index, & gte_normalize_sqr_tbl), add_u_self(r.sqrtbl_index, r.v_sqr_aligned),
@@ -326,7 +326,7 @@ MipsAtom_Proc_(aa, {
 		GteDelay_ load_word(R_AtomJmp, R_TapePtr, 0), LdSlot_   // ac_yield: word 1
 		GteDelay_ add_ui_self(         R_TapePtr, S_(MipsCode)) // ac_yield: word 2
 	),
-	mac_shift_aright_var_v3s4_self(r.res, r.half_shift),
+	mac_shift_aright_var_v3s4_self(r.res, r.srav_shift),
 	mac_store_v3s4(r.res, r.dst_ptr, 0),
 
 	jump_reg(R_AtomJmp), BdSlot_ nop // ac_yield: word 3-4

code/hello_camera/hello_camera.atom.c

@@ -288,23 +288,6 @@ internal MipsAtom_(screen_env_init) atom_info(atom_phase(screen_init)
 	mac_yield(),
 };
 
-/* gp_screen_init's GPR setup. Tests the mixed user-pinning + auto-reg pattern:
- *   - R_IO_BaseAddr = R_T4 (user-pinned via atom_reg; pre-existing)
- *   - R_GP1_Offset  = R_T2 (user-pinned via atom_reg; NEW -- for GPIO_PORT1_OFFSET)
- *   - R_ScreenX     = R_T5 (user-pinned via atom_reg; used as a transfer and GTE setup reg)
- *   - R_GpTmp       = auto-allocated by the lua pass and used for several GPU transfers;
- *                    the C preprocessor resolves it to the chosen free pool GPR.
- *
- * For gp_screen_init, the auto-reg pool exclusions are:
- *   user_pinned (from the corpus register_alias_registry) : R_T0..R_T7 (all 8 user-pinned across hello_camera.atom.c)
- *   body-parsed physical registers                         : aliases resolve through the registry;
- *                                                           the body uses R_ScreenX, not raw R_T5
- *   source_pool after both subtractions                   : {R_V0, R_V1} only
- *   R_GpTmp gets R_V0 (the first-fit choice). Its repeated GPU-transfer use proves that the
- *   auto-reg allocation is active while the R_ScreenX references prove the pinned alias is used.
- *   R_TapePtr (R_T9), R_AtomJmp (R_T8), R_AT are excluded from the POOL by construction in
- *   passes/auto_reg.lua -- see the "obvious exclusions" comment block at the top of that file.
- */
 enum {
 	R_IO_BaseAddr = R_T4 atom_reg, /* Caller-pinned: IO_BASE_ADDR = 0x1F800000 */
 	R_GP1_Offset  = R_T2 atom_reg, /* Caller-pinned: GPIO_PORT1_OFFSET = 0x10 */
@@ -545,11 +528,13 @@ MipsAtom_(cube_g4_face) atom_info(atom_phase(cube_g4),
 	load_half_u(R_T2, R_FaceCursor, 2 * S_(S2)),
 	// load_half_u(R_T3, R_FaceCursor, 3 * S_(S2)),
 
-	LdSlot_ mac_gte_load_tri_verts(R_VertBase, R_T0, R_T1, R_T2), GteDelay_ load_half_u(R_T3, R_FaceCursor, 3 * S_(S2)), LdSlot_
+	LdSlot_ mac_gte_load_tri_verts(R_VertBase, R_T0, R_T1, R_T2), 
-	GteDelay_ nop, gte_cmdw_rotate_translate_perspective_triple,
+		GteDelay_ load_half_u(R_T3, R_FaceCursor, 3 * S_(S2)), LdSlot_
+		GteDelay_ load_word(R_AtomJmp, R_TapePtr, 0),          LdSlot_ //ac_yield: word 2,
+	gte_cmdw_rotate_translate_perspective_triple,
 	gte_cmdw_nclip,
 
-	gte_mv_from_data_r(R_T0, C2_MAC0), GteDelay_ load_word(R_AtomJmp, R_TapePtr, 0), // ac_yield: word 1
+	gte_mv_from_data_r(R_T0, C2_MAC0), GteDelay_ add_ui_self(R_TapePtr, S_(MipsCode)), // ac_yield: word 1
 	branch_le_zero(R_T0, atom_offset(cull, cube_g4_face_exit)),
 		/* BD-slot: Write the prim tag (R_0=0; overwrites the legacy tag word in the prim_buffer).
 		 * If branch IS taken (face culled), the body is skipped and this 0-tag is stranded —
@@ -568,7 +553,7 @@ MipsAtom_(cube_g4_face) atom_info(atom_phase(cube_g4),
 		add_ui(      R_AT, R_0,  OrderingTbl_Len),
 		set_lt_u(    R_AT, R_T1, R_AT),
 
-		branch_equal(R_AT, R_0,  atom_offset(bounds_chk, cube_g4_face_exit)), BdSlot_ add_ui_self(R_TapePtr, S_(MipsCode)), // ac_yield: word 2
+		branch_equal(R_AT, R_0,  atom_offset(bounds_chk, cube_g4_face_exit)), BdSlot_ nop,
 			mac_insert_ot_tag(R_OtBase, R_PrimCursor, S_(Poly_G4)),
 			mac_format_g4_color(R_PrimCursor,
 				/* c0 magenta */ 0xFF, 0x00, 0xFF,
@@ -581,7 +566,7 @@ MipsAtom_(cube_g4_face) atom_info(atom_phase(cube_g4),
 atom_label(cube_g4_face_exit)
 	add_ui_self(R_PrimCursor, S_(Poly_G4)),     /* 9 words = Poly_G4 */
 	add_ui_self(R_FaceCursor, S_(S2) * 4),      /* 4 × S2 = 8 bytes */
-	jump_reg(R_TapePtr), BdSlot_ nop // ac_yield: word 3-4
+	jump_reg(R_AtomJmp), BdSlot_ nop      // ac_yield: word 3-4
 };
 
 typedef Struct_(Binds_FloorTri) {
@@ -638,7 +623,7 @@ MipsAtom_(floor_f3_face) atom_info(atom_phase(floor_f3)
 /* Advance Input Cursor & Yield (Both branch targets land here) */
 atom_label(floor_f3_face_exit)
 	add_ui_self(R_FaceCursor, S_(S2) * 4),  /* Advance Face Cursor (4 * S2 = 8 bytes) */
-	jump_reg(R_TapePtr), BdSlot_ nop // ac_yield: word 3-4
+	jump_reg(R_AtomJmp), BdSlot_ nop // ac_yield: word 3-4
 };
 
 typedef Struct_(Binds_SyncPrimitiveArena) { U4 used; U4 cursor; };