From 13a0b9dca458e84f4d0645189ef770b2ff73941a Mon Sep 17 00:00:00 2001 From: Ed_ Date: Sun, 5 Jul 2026 21:26:26 -0400 Subject: [PATCH] forcing myself to move forward, need to address missing annotations for "name bindings" on allocated registers. --- code/duffle/gcc_asm.h | 12 ++++++------ code/duffle/gte.h | 30 +++++++++++++++------------- code/duffle/lottes_tape.h | 40 +++++++++++++++++++------------------- code/duffle/mips.h | 22 ++++++++++----------- code/gte_hello/hello_gte.c | 7 ++++--- 5 files changed, 58 insertions(+), 53 deletions(-) diff --git a/code/duffle/gcc_asm.h b/code/duffle/gcc_asm.h index d9a7851..763229b 100644 --- a/code/duffle/gcc_asm.h +++ b/code/duffle/gcc_asm.h @@ -66,14 +66,15 @@ * register V3_S2* p0 rgcc(R_T4) = ...; // bundled * * asm volatile("nop" : : : reg_str(R_RA), "memory"); // clobber list */ -#define rlit_impl(n) "$" #n -#define rlit(n) rlit_impl(n) +#define rlit_stringfy(n) "$" stringify(n) +#define rlit_tmpl(n) rlit_stringfy(tmpl(n,Code)) +#define rlit(n) rlit_tmpl(n) /* ------------------------------------------------------------------------ * * rgcc(n) — GCC-specific bundle for register-variable declarations. * - * Produces `__asm__(reg_str(tmpl(n, MipsAtom)))` at expansion time. - * The `tmpl(n, MipsAtom)` indirection derives the preprocessor-visible `_Code` + * Produces `__asm__(reg_str(tmpl(n, MipsCode)))` at expansion time. + * The `tmpl(n, MipsCode)` indirection derives the preprocessor-visible `_Code` * form from the enum name (which the preprocessor can't expand on its own). * So a call is: register V3_S2* p rgcc(R_T4) = verts[0].ptr; * expands (via tmpl) to: register V3_S2* p __asm__(rlit(R_T4_Code)) = verts[0].ptr; @@ -91,8 +92,7 @@ * * For clobber lists and asm-template strings, use the bare `rlit(R_T4_Code)`. * ------------------------------------------------------------------------ */ -#define rgcc_(n) __asm__(rlit(tmpl(n, Code))) -#define rgcc(n) rgcc_(n) +#define rgcc(n) __asm__(rlit(n)) /* rgcc_ref(n) — GCC operand-reference form "%N". Not currently used * by the placeholder-pun macros (the .word bodies are fully baked diff --git a/code/duffle/gte.h b/code/duffle/gte.h index 0484a67..8a59a7d 100644 --- a/code/duffle/gte.h +++ b/code/duffle/gte.h @@ -132,7 +132,7 @@ enum { gte_in_v1_z = C2_VZ1, /* Input Vector 1 (Z) */ gte_in_v2_xy = C2_VXY2, /* Input Vector 2 (X, Y) */ gte_in_v2_z = C2_VZ2, /* Input Vector 2 (Z) */ - gte_in_rgb = C2_RGB, /* Input Color (R, G, B, MipsAtom) */ + gte_in_rgb = C2_RGB, /* Input Color (R, G, B, MipsCode) */ gte_out_scr_xy0 = C2_SXY0, /* Output Screen Coord 0 (X, Y) */ gte_out_scr_xy1 = C2_SXY1, /* Output Screen Coord 1 (X, Y) */ gte_out_scr_xy2 = C2_SXY2, /* Output Screen Coord 2 (X, Y) */ @@ -385,6 +385,10 @@ enum { _C2_OPS_ = 0 #define gte_cmdw_avsz3 (gte_cmd_base | enc_gte_cmd(gte_cmd_avsz3) | gte_cmdw_psyq_avsz3_compat) +/* AVSZ4 — average Z of 4 vertices (for quads) */ +#define gte_cmd_avsz4 0x2E +#define gte_cmdw_avsz4 (gte_cmd_base | enc_gte_cmd(gte_cmd_avsz4) | gte_cmdw_psyq_avsz3_compat) + /** * @brief Loads a single SVECTOR to GTE vector register V0 * @@ -460,22 +464,22 @@ enum { * * The `asm_clobber(...)` helper from gcc_asm.h prepends the colon that * starts the clobbers section. */ -#define gte_load_v0(r_ptr, base) asm volatile( \ +#define gte_load_v0(r_ptr, base) asm volatile( \ asm_words( gte_lw_v0(base), gte_lw_v0z(base) ) \ - asm_rpins, r_use(r_ptr) \ - asm_clobber: rlit(R_V0_Code), rlit(R_T0_Code), rlit(R_T1_Code), rlit(R_RA_Code), clb_mem_drain \ + asm_rpins, r_use(r_ptr) \ + asm_clobber: rlit(R_V0), rlit(R_T0), rlit(R_T1), rlit(R_RA), clb_mem_drain \ ) -#define gte_load_v1(r_ptr, base) asm volatile( \ +#define gte_load_v1(r_ptr, base) asm volatile( \ asm_words( gte_lw_v1(base), gte_lw_v1z(base) ) \ - asm_rpins, r_use(r_ptr) \ - asm_clobber: rlit(R_V0_Code), rlit(R_T0_Code), rlit(R_T1_Code), rlit(R_RA_Code), clb_mem_drain \ + asm_rpins, r_use(r_ptr) \ + asm_clobber: rlit(R_V0), rlit(R_T0), rlit(R_T1), rlit(R_RA), clb_mem_drain \ ) -#define gte_load_v2(r_ptr, base) asm volatile( \ - asm_words( gte_lw_v2(base), gte_lw_v2z(base) ) \ - asm_rpins, r_use(r_ptr) \ - asm_clobber: rlit(R_V0_Code), rlit(R_T0_Code), rlit(R_T1_Code), rlit(R_RA_Code), clb_mem_drain \ +#define gte_load_v2(r_ptr, base) asm volatile( \ + asm_words( gte_lw_v2(base), gte_lw_v2z(base) ) \ + asm_rpins, r_use(r_ptr) \ + asm_clobber: rlit(R_V0), rlit(R_T0), rlit(R_T1), rlit(R_RA), clb_mem_drain \ ) /* gte_load_v0v1v2(p0, p1, p2, b0, b1, b2) — the canonical prelude to gte_cmd_rtpt. @@ -497,7 +501,7 @@ enum { gte_lw_v2(b2), gte_lw_v2z(b2) ) \ asm_rpins \ , r_use(p0), r_use(p1), r_use(p2) \ - asm_clobber: rlit(R_V0_Code), rlit(R_T0_Code), rlit(R_T1_Code), rlit(R_RA_Code), clb_mem_drain \ + asm_clobber: rlit(R_V0), rlit(R_T0), rlit(R_T1), rlit(R_RA), clb_mem_drain \ ) /** @@ -650,5 +654,5 @@ enum { , gte_mt( R_T4, 4) \ ) \ , r_use(r0) \ - asm_clobber: clb_system, rlit(R_T4_Code), rlit(R_T5_Code), rlit(R_T6_Code) \ + asm_clobber: clb_system, rlit(R_T4), rlit(R_T5), rlit(R_T6) \ ) diff --git a/code/duffle/lottes_tape.h b/code/duffle/lottes_tape.h index e85aa50..2df9f2b 100644 --- a/code/duffle/lottes_tape.h +++ b/code/duffle/lottes_tape.h @@ -17,12 +17,14 @@ enum { R_TapePtr = R_T8, /* The Instruction Stream Pointer */ R_PrimCur = R_T7, /* VRAM output cursor (primitive buffer) */ R_FaceCur = R_T4, /* Input data cursor (indices/faces) */ + R_InCursor = R_T4, /* Input data cursor (indices/faces) */ R_VertBase = R_T5, /* Base address of the vertex array */ R_OtBase = R_T6, /* Base address of the Ordering Table */ /* Stringification codes for the GCC inline assembler clobber lists */ #define R_TapePtr_Code R_T8_Code #define R_PrimCur_Code R_T7_Code #define R_FaceCur_Code R_T4_Code +#define R_InCursor_Code R_T4_Code #define R_VertBase_Code R_T5_Code #define R_OtBase_Code R_T6_Code }; @@ -55,12 +57,12 @@ FI_ void tape_run(Slice_U4 tape) { register U4* tp rgcc(R_TapePtr) = tape.ptr; a ) asm_rpins, r_use(tp) asm_clobber: - rlit(R_AT_Code) - , rlit(R_V0_Code), rlit(R_V1_Code) - , rlit(R_T0_Code), rlit(R_T1_Code), rlit(R_T2_Code), rlit(R_T3_Code) + rlit(R_AT) + , rlit(R_V0), rlit(R_V1) + , rlit(R_T0), rlit(R_T1), rlit(R_T2), rlit(R_T3) /* Tell GCC the tape engine owns and destroys the workspace registers */ - , rlit(R_PrimCur_Code), rlit(R_FaceCur_Code), rlit(R_VertBase_Code), rlit(R_OtBase_Code) - , rlit(R_T9_Code) + , rlit(R_PrimCur), rlit(R_FaceCur), rlit(R_VertBase), rlit(R_OtBase) + , rlit(R_T9) , clb_mem_drain ); } @@ -68,7 +70,7 @@ typedef Struct_(TapeBuilder) { U4 ptr; U4 count; }; FI_ void tb_init(TapeBuilder* tb, FArena* arena) { tb->ptr = arena->start; tb->count = 0; } FI_ TapeBuilder tb_make( FArena* arena) { return (TapeBuilder){ arena->start, 0 }; } -FI_ void tb_emit(TapeBuilder* tb, MipsAtom* atom) { u4_r(tb->ptr)[tb->count] = u4_(atom); ++ tb->count; } +FI_ void tb_emit(TapeBuilder* tb, MipsCode* atom) { u4_r(tb->ptr)[tb->count] = u4_(atom); ++ tb->count; } FI_ void tb_data(TapeBuilder* tb, U4 data) { u4_r(tb->ptr)[tb->count] = u4_(data); ++ tb->count; } FI_ Slice_U4 tb_end (TapeBuilder* tb) { tb_emit(tb,code_tape_exit); return (Slice_U4){ C_(U4*,tb->ptr), tb->count }; } @@ -76,21 +78,21 @@ FI_ Slice_U4 tb_slice(TapeBuilder tb) { return (Sli #define tb_scope(tb) for(U4 tbs_once=0;tbs_once==0;++tbs_once,tb_emit(tb,code_tape_exit)) /* --------------------------------------------------------------------------- - * MACRO ATOMS (Reusable Assembly Components) + * MACRO ATOM Components (Reusable Assembly Components) * These do NOT yield. They are expanded inline inside Tape Atoms. * ---------------------------------------------------------------------------*/ /* Loads 3 16-bit indices from the face array */ -#define mac_load_tri_indices(r_idx0, r_idx1, r_idx2) \ - load_half_u(r_idx0, R_FaceCur, 0) \ - , load_half_u(r_idx1, R_FaceCur, 2) \ - , load_half_u(r_idx2, R_FaceCur, 4) +#define mac_load_tri_indices(rId_0, rId_1, rId_2) \ + load_half_u(rId_0, R_FaceCur, 0) \ + , load_half_u(rId_1, R_FaceCur, 2) \ + , load_half_u(rId_2, R_FaceCur, 4) /* Translates indices to vertex addresses and pushes them to GTE */ -#define mac_load_tri_verts(r_idx0, r_idx1, r_idx2) \ - shift_ll(R_AT, r_idx0, 3), add_u(R_AT, R_AT, R_VertBase), load_word(R_V0, R_AT, 0), load_word(R_V1, R_AT, 4), gte_mt(R_V0, C2_VXY0), gte_mt(R_V1, C2_VZ0) \ - , shift_ll(R_AT, r_idx1, 3), add_u(R_AT, R_AT, R_VertBase), load_word(R_V0, R_AT, 0), load_word(R_V1, R_AT, 4), gte_mt(R_V0, C2_VXY1), gte_mt(R_V1, C2_VZ1) \ - , shift_ll(R_AT, r_idx2, 3), add_u(R_AT, R_AT, R_VertBase), load_word(R_V0, R_AT, 0), load_word(R_V1, R_AT, 4), gte_mt(R_V0, C2_VXY2), gte_mt(R_V1, C2_VZ2) +#define mac_load_tri_verts(rId_0, rId_1, rId_2) \ + shift_ll(R_AT, rId_0, 3), add_u(R_AT, R_AT, R_VertBase), load_word(R_V0, R_AT, 0), load_word(R_V1, R_AT, 4), gte_mt(R_V0, C2_VXY0), gte_mt(R_V1, C2_VZ0) \ + , shift_ll(R_AT, rId_1, 3), add_u(R_AT, R_AT, R_VertBase), load_word(R_V0, R_AT, 0), load_word(R_V1, R_AT, 4), gte_mt(R_V0, C2_VXY1), gte_mt(R_V1, C2_VZ1) \ + , shift_ll(R_AT, rId_2, 3), add_u(R_AT, R_AT, R_VertBase), load_word(R_V0, R_AT, 0), load_word(R_V1, R_AT, 4), gte_mt(R_V0, C2_VXY2), gte_mt(R_V1, C2_VZ2) /* Formats the primitive memory layout (Tag + Color + Coordinates) */ #define mac_format_prim_f3(color_hi, color_lo) \ @@ -101,8 +103,6 @@ FI_ Slice_U4 tb_slice(TapeBuilder tb) { return (Sli , gte_sw(C2_SXY1, R_PrimCur, 12) \ , gte_sw(C2_SXY2, R_PrimCur, 16) - - /* Correctly inserts a primitive into the Ordering Table linked list */ #define mac_insert_ot_tag(r_otz, prim_length) \ shift_ll( R_T1, r_otz, 2) \ @@ -266,8 +266,8 @@ internal MipsAtom_(cube_tri) { /* Word 8: p3 = SXY0 (written AFTER RTPS with V3's screen coords) */ gte_sw(C2_SXY0, R_PrimCur, 32), - /* ── 9. AVSZ3 — average Z for OTZ (uses SZ1/SZ2/SZ3 from RTPT) ──────── */ - nop, nop, gte_cmdw_avsz3, + /* ── 9. AVSZ4 — average Z from SZ0/SZ1/SZ2/SZ3 ────────────── */ + nop, nop, gte_cmdw_avsz4, nop, nop, gte_mf(R_T1, C2_OTZ), @@ -330,7 +330,7 @@ internal MipsAtom_(diag_yield) { mips_yield() }; /* DIAGNOSTIC 2: Pure memory test (No GTE). Draws a fixed cyan triangle. */ internal MipsAtom_(diag_color) { store_word(R_0, R_T7, 0), - load_ui( R_AT, 0x20FF), /* High: MipsAtom 0x20 + Color B:FF */ + load_ui( R_AT, 0x20FF), /* High: MipsCode 0x20 + Color B:FF */ or_i( R_AT, R_AT, 0xFF00), /* Low: Color G:FF, R:00 (Cyan) */ store_word(R_AT, R_T7, 4), diff --git a/code/duffle/mips.h b/code/duffle/mips.h index 3d66be9..6882480 100644 --- a/code/duffle/mips.h +++ b/code/duffle/mips.h @@ -377,14 +377,14 @@ enum { _BitOffsets = 0 asm volatile( \ asm_words(load_ui((rt), u4_hi(imm), \ add_si((rt), (rt), (S2)C_(U2,u4_lo(imm))) \ - asm_clobber: rlit(R_AT_Code), clb_mem_drain \ + asm_clobber: rlit(R_AT), clb_mem_drain \ ); \ } \ else { \ asm volatile(asm_words( \ load_ui((rt), u4_hi(imm)), \ or_i((rt), (rt), C_(U2,u4_lo(imm)) \ - asm_clobber: rlit(R_AT_Code), clb_mem_drain \ + asm_clobber: rlit(R_AT), clb_mem_drain \ ); \ } \ } while (0) @@ -395,7 +395,7 @@ enum { _BitOffsets = 0 asm volatile( \ asm_words(load_ui((rt), u4_lo(imm)), \ or_i((rt), (rt), C_(U2,u4_hi(imm))) ) \ - asm_clobber: rlit(R_AT_Code), clb_mem_drain \ + asm_clobber: rlit(R_AT), clb_mem_drain \ ); \ } while (0) @@ -408,7 +408,7 @@ enum { _BitOffsets = 0 asm volatile(asm_words( \ lui_op((rt), u4_lo(imm)), \ add_si((rt), (rt), (S2)C_(U2,u4_hi(imm))) ) \ - asm_clobber: rlit(R_AT_Code), clb_mem_drain \ + asm_clobber: rlit(R_AT), clb_mem_drain \ ); \ } while (0) @@ -436,14 +436,14 @@ enum { _BitOffsets = 0 /* Small positive: addi rt, $0, imm */ \ asm volatile( \ asm_words(add_si((rt), R_0, (imm))) \ - asm_clobber: rlit(R_AT_Code), clb_mem_drain \ + asm_clobber: rlit(R_AT), clb_mem_drain \ ); \ } \ else if (cexpr_(imm) && ((U4)(imm) <= 0xFFFFU)) { \ /* 0x8000..0xFFFF: ori rt, $0, imm (zero-extends) */ \ asm volatile( \ asm_words(or_i((rt), R_0, (imm))) \ - asm_clobber: rlit(R_AT_Code), clb_mem_drain \ + asm_clobber: rlit(R_AT), clb_mem_drain \ ); \ } \ else \ @@ -455,14 +455,14 @@ enum { _BitOffsets = 0 asm volatile(asm_words( \ load_ui((rt), u4_hi(imm)), \ add_si((rt), (rt), (S2)C_(U2,u4_lo(imm))) \ - asm_clobber: rlit(R_AT_Code), clb_mem_drain \ + asm_clobber: rlit(R_AT), clb_mem_drain \ ); \ } \ else { \ asm volatile(asm_words( \ load_ui((rt), u4_hi(imm)), \ or_i((rt), (rt), C_(U2,u4_lo(imm)) \ - asm_clobber: rlit(R_AT_Code), clb_mem_drain \ + asm_clobber: rlit(R_AT), clb_mem_drain \ ); \ } \ } \ @@ -470,8 +470,8 @@ enum { _BitOffsets = 0 // Binary Metaprogramming -typedef U4 const MipsAtom; -#define MipsAtom_(sym) MipsAtom tmpl(code,sym) [] align_(4) = +typedef U4 const MipsCode; +#define MipsAtom_(sym) MipsCode tmpl(code,sym) [] align_(4) = enum { bios_flushcache = 0x44, @@ -506,7 +506,7 @@ I_ void mips_flush_icache(void) { C_(VoidFn*, code_mips_flush_icache)(); } * GPRs that the kernel treats as volatile (v0/v1/t0/t1/ra) plus the * "memory" barrier. The register ids are passed through `rlit` so * the R_*_Code `#define`s are stringified into "$N" at expansion time. */ -#define clb_system rlit(R_V0_Code), rlit(R_T0_Code), rlit(R_T1_Code), rlit(R_RA_Code), clb_mem_drain +#define clb_system rlit(R_V0), rlit(R_T0), rlit(R_T1), rlit(R_RA), clb_mem_drain #define asm_mips_flush_icache() asm volatile( asm_words( \ add_ui(rstack_ptr, rstack_ptr, -8) \ diff --git a/code/gte_hello/hello_gte.c b/code/gte_hello/hello_gte.c index 0971d30..f6f0673 100644 --- a/code/gte_hello/hello_gte.c +++ b/code/gte_hello/hello_gte.c @@ -191,7 +191,7 @@ void update(PrimitiveArena* pa, U4* ordering_buf) S4 flag; //???? // Draw Cube - if (0) + if (1) { m3s2_rotation (& static_mem.cube.rot, & static_mem.tform_world); m3s2_translation(& static_mem.tform_world, & static_mem.cube.pos); @@ -230,8 +230,8 @@ void update(PrimitiveArena* pa, U4* ordering_buf) // static_mem.cube.rot.z += 12; static_mem.cube.rot.y += 30; } - // Draw cube (tape method) - if (1) + // Draw cube (tape method) - two triangles per face + if (0) { m3s2_rotation (& static_mem.cube.rot, & static_mem.tform_world); m3s2_translation(& static_mem.tform_world, & static_mem.cube.pos); @@ -251,6 +251,7 @@ void update(PrimitiveArena* pa, U4* ordering_buf) tb_data(& tb, u4_(ordering_buf)); for (U4 i = 0; i < Cube_num_faces; i++) { + // Two triangles per quad face: (x,y,z) and (x,z,w) tb_emit(& tb, code_cube_tri); }