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https://github.com/Ed94/pikuma_ps1.git
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+66
-62
@@ -8,95 +8,99 @@
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/* C2 data registers */
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/* --- GTE Data Registers (Coprocessor 2) --- */
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typedef enum {
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C2_VXY0 = 0, C2_VZ0 = 1, C2_VXY1 = 2, C2_VZ1 = 3,
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C2_VXY2 = 4, C2_VZ2 = 5, C2_RGB = 6, C2_OTZ = 7,
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C2_IR0 = 8, C2_IR1 = 9, C2_IR2 = 10, C2_IR3 = 11,
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C2_SXY0 = 12, C2_SXY1 = 13, C2_SXY2 = 14, C2_SXYP = 15,
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C2_SZ0 = 16, C2_SZ1 = 17, C2_SZ2 = 18, C2_SZ3 = 19,
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C2_RGB0 = 20, C2_RGB1 = 21, C2_RGB2 = 22, C2_RES1 = 23,
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C2_MAC0 = 24, C2_MAC1 = 25, C2_MAC2 = 26, C2_MAC3 = 27,
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C2_IRGB = 28, C2_ORGB = 29, C2_LZCS = 30, C2_LZCR = 31
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enum {
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C2_VXY0 = 0, C2_VZ0 = 1, C2_VXY1 = 2, C2_VZ1 = 3,
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C2_VXY2 = 4, C2_VZ2 = 5, C2_RGB = 6, C2_OTZ = 7,
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C2_IR0 = 8, C2_IR1 = 9, C2_IR2 = 10, C2_IR3 = 11,
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C2_SXY0 = 12, C2_SXY1 = 13, C2_SXY2 = 14, C2_SXYP = 15,
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C2_SZ0 = 16, C2_SZ1 = 17, C2_SZ2 = 18, C2_SZ3 = 19,
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C2_RGB0 = 20, C2_RGB1 = 21, C2_RGB2 = 22, C2_RES1 = 23,
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C2_MAC0 = 24, C2_MAC1 = 25, C2_MAC2 = 26, C2_MAC3 = 27,
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C2_IRGB = 28, C2_ORGB = 29, C2_LZCS = 30, C2_LZCR = 31
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};
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/* Semantic Aliases for GTE Data Registers */
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#define GTE_IN_VEC0_XY C2_VXY0 /* Input Vector 0 (X, Y) */
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#define GTE_IN_VEC0_Z C2_VZ0 /* Input Vector 0 (Z) */
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#define GTE_IN_VEC1_XY C2_VXY1 /* Input Vector 1 (X, Y) */
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#define GTE_IN_VEC1_Z C2_VZ1 /* Input Vector 1 (Z) */
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#define GTE_IN_VEC2_XY C2_VXY2 /* Input Vector 2 (X, Y) */
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#define GTE_IN_VEC2_Z C2_VZ2 /* Input Vector 2 (Z) */
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#define GTE_IN_COLOR C2_RGB /* Input Color (R, G, B, Code) */
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#define GTE_OUT_SCR_XY0 C2_SXY0 /* Output Screen Coord 0 (X, Y) */
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#define GTE_OUT_SCR_XY1 C2_SXY1 /* Output Screen Coord 1 (X, Y) */
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#define GTE_OUT_SCR_XY2 C2_SXY2 /* Output Screen Coord 2 (X, Y) */
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#define GTE_OUT_DEPTH C2_OTZ /* Output Ordering Table Z (Depth) */
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#define GTE_MATH_ACCUM0 C2_MAC0 /* Math Accumulator 0 */
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#define GTE_MATH_ACCUM1 C2_MAC1 /* Math Accumulator 1 */
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#define GTE_MATH_ACCUM2 C2_MAC2 /* Math Accumulator 2 */
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enum {
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gte_in_v0_xy = C2_VXY0, /* Input Vector 0 (X, Y) */
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gte_in_v0_z = C2_VZ0, /* Input Vector 0 (Z) */
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gte_in_v1_xy = C2_VXY1, /* Input Vector 1 (X, Y) */
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gte_in_v1_z = C2_VZ1, /* Input Vector 1 (Z) */
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gte_in_v2_xy = C2_VXY2, /* Input Vector 2 (X, Y) */
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gte_in_v2_z = C2_VZ2, /* Input Vector 2 (Z) */
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gte_in_rgb = C2_RGB, /* Input Color (R, G, B, Code) */
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gte_out_scr_xy0 = C2_SXY0, /* Output Screen Coord 0 (X, Y) */
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gte_out_scr_xy1 = C2_SXY1, /* Output Screen Coord 1 (X, Y) */
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gte_out_scr_xy2 = C2_SXY2, /* Output Screen Coord 2 (X, Y) */
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gte_out_depth = C2_OTZ, /* Output Ordering Table Z (Depth) */
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gte_math_accum0 = C2_MAC0, /* Math Accumulator 0 */
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gte_math_accum1 = C2_MAC1, /* Math Accumulator 1 */
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gte_math_accum2 = C2_MAC2, /* Math Accumulator 2 */
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};
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/* --- GTE Command Semantics (The Bitfield Meanings) ---
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* A GTE command is a single 32-bit word sent to COP2.
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* It is highly configurable via bitfields.
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*/
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enum {
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/* Shift Fraction (Bit 19) - Determines fixed-point division */
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#define GTE_SF_FRACTIONAL 0 /* Divide result by 4096 (Standard 4.12 fixed point) */
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#define GTE_SF_INTEGER 1 /* No division (Raw integer math) */
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gte_sf_fractional = 0, /* Divide result by 4096 (Standard 4.12 fixed point) */
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gte_sf_integer = 1, /* No division (Raw integer math) */
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/* Matrix Select (Bits 18-17) - Which 3x3 matrix to multiply by */
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#define GTE_MX_ROTATION 0 /* Rotation Matrix (RT) */
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#define GTE_MX_LIGHT 1 /* Light Matrix (LL) */
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#define GTE_MX_COLOR 2 /* Color Matrix (LC) */
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#define GTE_MX_NONE 3 /* Reserved / Do not multiply */
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/* Vector Select (Bits 16-15) - Which input vector to use */
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#define GTE_V_VEC0 0 /* Use Vector 0 (VXY0, VZ0) */
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#define GTE_V_VEC1 1 /* Use Vector 1 (VXY1, VZ1) */
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#define GTE_V_VEC2 2 /* Use Vector 2 (VXY2, VZ2) */
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#define GTE_V_IR_REGS 3 /* Use Intermediate Registers (IR1, IR2, IR3) */
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gte_mx_rotation = 0, /* Rotation Matrix (RT) */
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gte_mx_light = 1, /* Light Matrix (LL) */
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gte_mx_color = 2, /* Color Matrix (LC) */
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gte_mx_none = 3, /* Reserved / Do not multiply */
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/* Vector select (Bits 16-15) - Which input vector to use */
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gte_v_v0 = 0, /* Use Vector 0 (VXY0, VZ0) */
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gte_v_v1 = 1, /* Use Vector 1 (VXY1, VZ1) */
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gte_v_v2 = 2, /* Use Vector 2 (VXY2, VZ2) */
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gte_v_ir_regs = 3, /* Use Intermediate Registers (IR1, IR2, IR3) */
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/* Control Vector Select (Bits 14-13) - Which vector to ADD after multiplication */
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#define GTE_CV_TRANSLATE 0 /* Add Translation Vector (TRX, TRY, TRZ) */
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#define GTE_CV_BG_COLOR 1 /* Add Background Color (RBK, GBK, BBK) */
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#define GTE_CV_FAR_COLOR 2 /* Add Far Color (RFC, GFC, BFC) */
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#define GTE_CV_NONE 3 /* Add Zero (No addition) */
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gte_cv_translate = 0, /* Add Translation Vector (TRX, TRY, TRZ) */
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gte_cv_bg_color = 1, /* Add Background Color (RBK, GBK, BBK) */
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gte_cv_far_color = 2, /* Add Far Color (RFC, GFC, BFC) */
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gte_cv_none = 3, /* Add Zero (No addition) */
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/* Limit/Clamp (Bit 10) - Prevents overflow artifacts */
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#define GTE_LM_NORMAL 0 /* Normal math (can overflow) */
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#define GTE_LM_CLAMP 1 /* Clamp results to valid hardware ranges (e.g., RGB 0-255) */
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gte_lm_normal = 0, /* Normal math (can overflow) */
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gte_lm_clamp = 1, /* Clamp results to valid hardware ranges (e.g., RGB 0-255) */
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/* Core Command IDs (Bits 5-0) */
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#define GTE_CMD_RTPS 0x01 /* Rot/Trans Perspective Single (1 vertex) */
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#define GTE_CMD_RTPT 0x02 /* Rot/Trans Perspective Triple (3 vertices) */
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#define GTE_CMD_NCLIP 0x06 /* Normal Clipping (Backface culling) */
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#define GTE_CMD_OP 0x0C /* Outer Product */
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#define GTE_CMD_MVMVA 0x12 /* Matrix Vector Multiply & Add (Custom math) */
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gte_cmd_rtps = 0x01, /* Rot/Trans Perspective Single (1 vertex) */
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gte_cmd_rtpt = 0x02, /* Rot/Trans Perspective Triple (3 vertices) */
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gte_cmd_nclip = 0x06, /* Normal Clipping (Backface culling) */
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gte_cmd_op = 0x0C, /* Outer Product */
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gte_cmd_mvmva = 0x12, /* Matrix Vector Multiply & Add (Custom math) */
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};
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/* COP2 (GTE) Transfer Format
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* Opcode is always MIPS_OP_COP2. The 'sub' field determines direction (MT/MF). */
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#define ENC_COP2_TX(sub, rt, rd) \
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((MIPS_OP_COP2 << MIPS_OPCODE_SHIFT) | \
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(((sub) & MIPS_REG_MASK) << MIPS_RS_SHIFT) | \
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(((rt) & MIPS_REG_MASK) << MIPS_RT_SHIFT) | \
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(((rd) & MIPS_REG_MASK) << MIPS_RD_SHIFT))
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* Opcode is always op_cop2. The 'sub' field determines direction (MT/MF). */
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#define enc_cop2_tx(sub, rt, rd) enc_op(op_cop2) | enc_rs(sub) | enc_rt(rt) | enc_rd(rd)
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/* GTE Command Format (The math engine trigger)
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* Opcode is always MIPS_OP_COP2, RS is always 1 (CO).
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* The lower 25 bits are the GTE-specific command payload. */
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#define GTE_CMD_BASE ((MIPS_OP_COP2 << MIPS_OPCODE_SHIFT) | (1 << 25))
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#define ENC_GTE_CMD(sf, mx, v, cv, lm, cmd) \
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(GTE_CMD_BASE | \
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#define gte_cmd_base (enc_op(op_cop2) | (1 << 25))
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#define ENC_GTE_CMD(sf, mx, v, cv, lm, cmd) (gte_cmd_base | \
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(((sf) & 1) << 19) | (((mx) & 3) << 17) | (((v) & 3) << 15) | \
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(((cv) & 3) << 13) | (((lm) & 1) << 10) | ((cmd) & 0x3F))
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#define asm_gte_matrix_set_rotation asm volatile( \
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asm_inline( \
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\
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) \
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asm_clobber() \
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)
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// #define asm_gte_matrix_set_rotation asm volatile( \
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// asm_inline( \
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// \
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// ) \
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// asm_clobber() \
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// )
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+2
-8
@@ -143,12 +143,7 @@ enum { _BitOffsets = 0
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#define enc_i(op, rs, rt, imm) (enc_op(op) | enc_rs(rs) | enc_rt(rt) | enc_imm(imm))
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/* COP0 (System) Transfer Format */
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#define ENC_COP0_TX(sub, rt, rd) \
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((MIPS_OP_COP0 << MIPS_OPCODE_SHIFT) | \
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(((sub) & MIPS_REG_MASK) << MIPS_RS_SHIFT) | \
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(((rt) & MIPS_REG_MASK) << MIPS_RT_SHIFT) | \
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(((rd) & MIPS_REG_MASK) << MIPS_RD_SHIFT))
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#define enc_cop0_tx(sub, rt, rd) enc_op(op_cop0) | enc_rs(sub) | enc_rt(rt) | enc_rd(rd)
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/* COP0 Return From Exception (rfe) */
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#define enc_rfe() 0x42000010
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@@ -209,8 +204,7 @@ FI_ void mips_flush_icache(void) { C_(VoidFn*, codeblob_mips_flush_icache)(); }
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asm_clobber( clb_system ) \
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)
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void test()
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{
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void test_mips_asm() {
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asm_mips_flush_icache();
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}
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