mirror of
https://github.com/Ed94/pikuma_ps1.git
synced 2026-08-04 06:38:48 +00:00
just do regular varadic subst, adjusting annotation convention
This commit is contained in:
+46
-48
@@ -18,7 +18,7 @@
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* R_T7 = R_T7_Code, // in the enum
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*
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* User code should always reference the enum form (`R_T4`) at arithmetic
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* sites and let `reg_str(R_T4_Code)` / `rgcc(R_T4)` handle the stringify
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* sites and let `rlit(R_T4_Code)` / `rgcc(R_T4)` handle the stringify
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* cases — never write the bare number `12`.
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* ============================================================================ */
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#define R_0_Code 0
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@@ -366,42 +366,42 @@ enum { _BitOffsets = 0
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U4 _li2_hi_ = _li2_imm_ >> 16; \
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if (_li2_lo_ <= 0x7FFFU) { \
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asm volatile( \
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asm_inline(lui_op((rt), _li2_hi_), \
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add_si((rt), (rt), (S2)(U2)_li2_lo_)) \
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asm_clobber(reg_str(R_AT_Code), "memory") \
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asm_words(lui_op((rt), _li2_hi_), \
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add_si((rt), (rt), (S2)(U2)_li2_lo_)) \
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asm_clobber(rlit(R_AT_Code), "memory") \
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); \
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} \
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else { \
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asm volatile( \
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asm_inline(lui_op((rt), _li2_hi_), \
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ori_op((rt), (rt), (U2)_li2_lo_)) \
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asm_clobber(reg_str(R_AT_Code), "memory") \
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asm_words(lui_op((rt), _li2_hi_), \
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ori_op((rt), (rt), (U2)_li2_lo_)) \
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asm_clobber(rlit(R_AT_Code), "memory") \
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); \
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} \
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} while (0)
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/* load_imm_2w_ori — force the `lui` + `ori` form regardless of lo16 sign.
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* Use when you specifically need zero-extension in the lo half. */
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#define load_imm_2w_ori(rt, imm) do { \
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U4 _li2o_imm_ = (U4)(imm); \
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asm volatile( \
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asm_inline(lui_op((rt), _li2o_imm_ >> 16), \
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ori_op((rt), (rt), (U2)(_li2o_imm_ & 0xFFFFU))) \
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asm_clobber(reg_str(R_AT_Code), "memory") \
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); \
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#define load_imm_2w_ori(rt, imm) do { \
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U4 _li2o_imm_ = (U4)(imm); \
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asm volatile( \
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asm_words(lui_op((rt), _li2o_imm_ >> 16), \
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ori_op((rt), (rt), (U2)(_li2o_imm_ & 0xFFFFU))) \
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asm_clobber(rlit(R_AT_Code), "memory") \
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); \
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} while (0)
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/* load_imm_2w_addi — force the `lui` + `addi` form regardless of lo16 sign.
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* Use when you know sign-extension is fine (e.g. lo16 is treated as
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* signed downstream) and you want a smaller effective instruction
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* (the assembler/MIPS hardware will sign-extend the imm16). */
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#define load_imm_2w_addi(rt, imm) do { \
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U4 _li2a_imm_ = (U4)(imm); \
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asm volatile( \
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asm_inline(lui_op((rt), _li2a_imm_ >> 16), \
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add_si((rt), (rt), (S2)(U2)(_li2a_imm_ & 0xFFFFU))) \
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asm_clobber(reg_str(R_AT_Code), "memory") \
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); \
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#define load_imm_2w_addi(rt, imm) do { \
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U4 _li2a_imm_ = (U4)(imm); \
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asm volatile( \
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asm_words(lui_op((rt), _li2a_imm_ >> 16), \
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add_si((rt), (rt), (S2)(U2)(_li2a_imm_ & 0xFFFFU))) \
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asm_clobber(rlit(R_AT_Code), "memory") \
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); \
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} while (0)
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/* load_imm rt, imm — true `li` semantics (assembler `li` pseudo)
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@@ -427,37 +427,36 @@ enum { _BitOffsets = 0
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if (__builtin_constant_p(imm) && ((U4)(imm) <= 0x7FFFU)) { \
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/* Small positive: addi rt, $0, imm */ \
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asm volatile( \
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asm_inline(add_si((rt), R_0, (imm))) \
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asm_clobber(reg_str(R_AT_Code), "memory") \
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asm_words(add_si((rt), R_0, (imm))) \
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asm_clobber(rlit(R_AT_Code), "memory") \
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); \
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} \
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else if (__builtin_constant_p(imm) && ((U4)(imm) <= 0xFFFFU)) { \
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/* 0x8000..0xFFFF: ori rt, $0, imm (zero-extends) */ \
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asm volatile( \
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asm_inline(ori_op((rt), R_0, (imm))) \
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asm_clobber(reg_str(R_AT_Code), "memory") \
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asm_words(ori_op((rt), R_0, (imm))) \
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asm_clobber(rlit(R_AT_Code), "memory") \
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); \
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} \
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else \
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{ \
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/* > 16 bits: lui + (ori | addi). \
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* If lo16 is in [0, 0x7FFF] use addi (sign-ext is harmless \
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* since the high half cleared bits 15..0). Otherwise ori. */ \
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* If lo16 is in [0, 0x7FFF] use addi (sign-ext is harmless \
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* since the high half cleared bits 15..0). Otherwise ori. */ \
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U4 _li_imm_ = (U4)(imm); \
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U4 _li_lo_ = _li_imm_ & 0xFFFFU; \
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U4 _li_hi_ = _li_imm_ >> 16; \
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if (_li_lo_ <= 0x7FFFU) { \
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asm volatile( \
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asm_inline(lui_op((rt), _li_hi_), \
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asm volatile(asm_words( \
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lui_op((rt), _li_hi_), \
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add_si((rt), (rt), (S2)(U2)_li_lo_)) \
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asm_clobber(reg_str(R_AT_Code), "memory") \
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asm_clobber(rlit(R_AT_Code), "memory") \
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); \
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} \
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else { \
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asm volatile( \
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asm_inline(lui_op((rt), _li_hi_), \
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ori_op((rt), (rt), (U2)_li_lo_)) \
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asm_clobber(reg_str(R_AT_Code), "memory") \
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asm volatile(asm_words( \
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lui_op((rt), _li_hi_), ori_op((rt), (rt), (U2)_li_lo_)) \
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asm_clobber: rlit(R_AT_Code), "memory" \
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); \
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} \
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} \
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@@ -486,26 +485,25 @@ enum {
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*/
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internal
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Code CodeBlob_(mips_flush_icache) {
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add_ui(rstack_ptr, rstack_ptr, -8), /* sp -= 8 */
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store_word(rret_addr, rstack_ptr, 4), /* sw $ra, 4($sp) */
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add_ui(rret_0, rdiscard, bios_flushcache), /* addiu $a0, $0, 0x44 */
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add_ui(rtmp_0, rdiscard, bios_table_addr), /* addiu $t0, $0, 0xA0 */
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jump_link(rtmp_0, rret_addr), /* jalr $t0, $ra */
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nop, /* BD slot */
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load_word(rret_addr, rstack_ptr, 4), /* lw $ra, 4($sp) */
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jump_reg(rret_addr), /* jr $ra */
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add_ui(rstack_ptr, rstack_ptr, 8) /* sp += 8 (BD) */
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add_ui(rstack_ptr, rstack_ptr, -8) /* sp -= 8 */
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, store_word(rret_addr, rstack_ptr, 4) /* sw $ra, 4($sp) */
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, add_ui(rret_0, rdiscard, bios_flushcache) /* addiu $a0, $0, 0x44 */
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, add_ui(rtmp_0, rdiscard, bios_table_addr) /* addiu $t0, $0, 0xA0 */
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, jump_link(rtmp_0, rret_addr) /* jalr $t0, $ra */
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, nop /* BD slot */
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, load_word(rret_addr, rstack_ptr, 4) /* lw $ra, 4($sp) */
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, jump_reg(rret_addr) /* jr $ra */
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, add_ui(rstack_ptr, rstack_ptr, 8) /* sp += 8 (BD) */
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};
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FI_ void mips_flush_icache(void) { C_(VoidFn*, codeblob_mips_flush_icache)(); }
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/* Standard clobber list for pure-MIPS asm volatile blocks: caller-saved
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* GPRs that the kernel treats as volatile (v0/v1/t0/t1/ra) plus the
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* "memory" barrier. The register ids are passed through `reg_str` so
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* "memory" barrier. The register ids are passed through `rlit` so
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* the R_*_Code `#define`s are stringified into "$N" at expansion time. */
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#define clb_system \
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rlit(R_V0_Code), rlit(R_T0_Code), rlit(R_T1_Code), rlit(R_RA_Code), "memory"
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#define clb_system rlit(R_V0_Code), rlit(R_T0_Code), rlit(R_T1_Code), rlit(R_RA_Code), "memory"
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#define asm_mips_flush_icache() asm volatile( asm_inline( \
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#define asm_mips_flush_icache() asm volatile( asm_words( \
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add_ui(rstack_ptr, rstack_ptr, -8) \
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, store_word(rret_addr, rstack_ptr, 4) \
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, add_ui(rret_0, rdiscard, bios_flushcache) \
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@@ -515,7 +513,7 @@ FI_ void mips_flush_icache(void) { C_(VoidFn*, codeblob_mips_flush_icache)(); }
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, load_word(rret_addr, rstack_ptr, 4) \
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, jump_reg(rret_addr) \
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, add_ui(rstack_ptr, rstack_ptr, 8) \
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) asm_clobber( clb_system ) )
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) asm_clobber: clb_system )
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void test_mips_asm() {
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asm_mips_flush_icache();
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