mirror of
https://github.com/Ed94/perfaware.git
synced 2024-09-20 04:57:32 -07:00
757 lines
13 KiB
C++
757 lines
13 KiB
C++
#include "bloat.hpp"
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// Octal formatting is used heavily throughout
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// See: https://gist.github.com/seanjensengrey/f971c20d05d4d0efc0781f2f3c0353da
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// (x86 is an octal machine)
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namespace Op
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{
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ct u8 Mask = 00210;
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ct u8 Mask_Low = 0b11110000;
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ct u8 Mask_High = 0b00001111;
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ct u8 Mask_Imme = 0b00111000;
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#define D_Opcodes \
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D_Entry( mov_RM_R ) \
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D_Entry( mov_Im_RM ) \
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D_Entry( mov_Im_R ) \
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D_Entry( mov_M_Acc ) \
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D_Entry( mov_Acc_M ) \
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D_Entry( mov_RM_SR ) \
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D_Entry( mov_SR_RM ) \
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enum Code : u8
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{
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mov_RM_R = 0b10001000,
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mov_Im_RM = 0b11001100,
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mov_Im_R = 0b10110000,
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mov_M_Acc = 0b10100000,
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mov_Acc_M = 0b10100010,
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mov_RM_SR = 0b10001110,
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mov_SR_RM = 0b10001100
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};
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char const* str( Code type )
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{
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switch ( type )
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{
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#define D_Entry( Entry_ ) \
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case Entry_: \
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return ZPL_STRINGIFY(Entry_); \
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D_Opcodes
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#undef D_Entry
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}
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return Msg_Invalid_Value;
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}
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char const* meumonic( Code type )
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{
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switch ( type )
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{
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case mov_RM_R :
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case mov_Im_RM :
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case mov_Im_R :
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case mov_M_Acc :
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case mov_Acc_M :
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case mov_RM_SR :
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case mov_SR_RM :
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return "mov";
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}
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return Msg_Invalid_Value;
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}
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char const* intuitive( Code type )
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{
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switch ( type )
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{
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case mov_RM_R :
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case mov_Im_RM :
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case mov_Im_R :
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case mov_M_Acc :
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case mov_Acc_M :
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case mov_RM_SR :
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case mov_SR_RM :
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return "move";
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}
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return Msg_Invalid_Value;
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}
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#undef D_Opcodes
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}
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namespace Field
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{
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inline
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u8 offset_left_reg( u8 reg )
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{
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return reg << 3;
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}
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// https://i.imgur.com/drsyYnM.png
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enum Direction : u8
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{
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Mask_Dir = 0b00000010,
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Dir_Src = 0b00,
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Dir_Dest = 0b10,
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};
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inline
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char const* str_direction( Direction direction )
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{
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switch ( direction )
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{
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case Dir_Dest:
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return "Destination";
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case Dir_Src:
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return "Source";
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}
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return Msg_Invalid_Value;
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}
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// https://i.imgur.com/9Op8Lnd.png
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enum Width : u8
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{
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Mask_Width = 0b00000001,
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Mask_Width_Imme = 0b00001000,
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Width_Byte = 0b00,
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Width_Word = 0b01,
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};
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inline
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char const* str_width( Width width )
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{
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switch ( width )
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{
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case Width_Byte:
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return "Byte";
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case Width_Word:
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return "Word";
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}
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return Msg_Invalid_Value;
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}
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// https://i.imgur.com/Job2oPd.png
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enum Mode : u8
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{
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Mask_Mode = 0b11000000,
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Mode_Mem = 0b00000000,
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Mode_Mem8 = 0b01000000,
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Mode_Mem16 = 0b10000000,
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Mode_Reg = 0b11000000,
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};
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char const* str_mode( Mode mode )
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{
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switch (mode)
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{
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case Mode_Mem:
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return "Memory: No Displacement";
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case Mode_Mem8:
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return "Memory: 8-bit Displacment";
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case Mode_Mem16:
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return "Memory: 16-bit Displacement";
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case Mode_Reg:
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return "Register";
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}
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return Msg_Invalid_Value;
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}
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ct u8 Mask_Memory = 0b00000111;
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// https://i.imgur.com/Tm5roJu.png
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enum Memory : u8
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{
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Add_BX_SI = 0b000,
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Add_BX_DI = 0b001,
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Add_BP_SI = 0b010,
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Add_BP_DI = 0b011,
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Add_SI = 0b100,
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Add_DI = 0b101,
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Add_Direct = 0b110,
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Add_BX = 0b111,
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Num_Memory
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};
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char const* str_memory( Memory mem )
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{
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char const* mem_to_str[Num_Memory] =
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{
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"BX + SI",
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"BX + DI",
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"BP + SI",
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"BP + DI",
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"SI",
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"DI",
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"BP",
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"BX"
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};
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return mem_to_str[ mem ];
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}
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char const* str_memory_intuitive( Memory mem )
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{
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char const* mem_to_str[Num_Memory] =
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{
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"Base.16 + Stack.Index",
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"Base.16 + Destination.Index",
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"Stack.Base + Stack.Index",
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"Stack.Base + Destination.Index",
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"Stack.Index",
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"Destination.Index",
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"Stack.Base",
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"BX"
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};
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return mem_to_str[ mem ];
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}
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}
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namespace Register
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{
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ct u8 Mask_Imme = 0b00000111;
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ct u8 Mask_Left = 0b00111000;
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ct u8 Mask_Right = 0b00000111;
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#define D_Opcodes \
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D_Entry( AL ) \
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D_Entry( CL ) \
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D_Entry( DL ) \
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D_Entry( BL ) \
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D_Entry( AH ) \
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D_Entry( CH ) \
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D_Entry( DH ) \
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D_Entry( BH ) \
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D_Entry( AX ) \
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D_Entry( CX ) \
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D_Entry( DX ) \
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D_Entry( BX ) \
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D_Entry( SP ) \
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D_Entry( BP ) \
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D_Entry( SI ) \
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D_Entry( DI ) \
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enum Type : u8
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{
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AL = 0b000,
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CL = 0b001,
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DL = 0b010,
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BL = 0b011,
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AH = 0b100,
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CH = 0b101,
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DH = 0b110,
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BH = 0b111,
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AX = 0b000,
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CX = 0b001,
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DX = 0b010,
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BX = 0b011,
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SP = 0b100,
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BP = 0b101,
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SI = 0b110,
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DI = 0b111,
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Num = 16
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};
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char const* meumonic( Type type, u8 Width )
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{
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static char const*
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Type_To_Meumonic[ Num ] =
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{
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#define D_Entry( Entry_ ) #Entry_,
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D_Opcodes
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#undef D_Entry
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};
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return Type_To_Meumonic[ type + Width * ( 7 + 1 ) ];
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}
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char const* intuitive( Type type, u8 Width )
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{
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static char const*
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Type_To_Intuitive[ Num ] =
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{
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"Accumulator.Low",
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"Count.Low",
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"Data.Low",
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"Base.Low",
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"Accumulator.High",
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"Count.High",
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"Data.High",
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"Base.High",
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"Accumulator.16",
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"Count.16",
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"Data.16",
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"Base.16",
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"Stack.Pointer",
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"Stack.Base",
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"Source.Index",
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"Destination.Index",
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};
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return Type_To_Intuitive[ type + Width * ( 7 + 1 ) ];
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}
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}
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struct Octal
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{
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u8 Low : 3;
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u8 High : 3;
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u8 Dir : 1;
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u8 Write : 1;
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operator u8()
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{
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return * cast( u8*, this);
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}
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};
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struct POD_Instruction
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{
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// 8086 Instructions are 1 to 6 bytes in length.
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union
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{
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u8* Ptr;
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u8 Byte[6];
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Octal Instr;
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struct
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{
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u8 Pad[2];
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u16_Split Disp;
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u16_Split Data;
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}
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EffAddr;
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struct
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{
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u8 Pad[1];
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u16_Split Data;
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}
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Imme;
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struct
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{
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u8 Pad;
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u16_Split Data;
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}
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Addr;
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};
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// If directly referencing blob data:
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// Part of next instruction, do not use as stratch memory.
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u16 Pad;
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};
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struct Instruction : public POD_Instruction
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{
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using Code = Op::Code;
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using Direction = Field::Direction;
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using Mode = Field::Mode;
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using Memory = Field::Memory;
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using Width = Field::Width;
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using Reg = Register::Type;
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inline
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Direction get_direction()
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{
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Direction direction = cast(Direction, Byte[0] & Field::Mask_Dir);
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return direction;
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}
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inline
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Mode get_mode()
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{
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Mode mode = cast( Mode, Byte[1] & Field::Mask_Mode );
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return mode;
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}
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inline
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Code get_opcode( u8 mask )
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{
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Op::Code opcode = cast( Op::Code, Byte[0] & mask );
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return opcode;
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}
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inline
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Width get_width( u8 mask )
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{
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Width width = cast( Width, Byte[0] & mask );
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return width;
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}
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inline
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Reg mode_operand_left_reg()
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{
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u8
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operand = Byte[1] & Register::Mask_Left;
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operand >>= 3;
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return cast(Reg, operand);
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}
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inline
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Reg mode_operand_right_reg()
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{
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u8 operand = Byte[1] & Register::Mask_Right;
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return cast( Reg, operand );
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}
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forceinline
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void dissassemble_mode( char const*& str_operand, Width& width, u8& length )
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{
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using namespace Field;
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using namespace Op;
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using namespace Register;
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switch ( get_mode() )
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{
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case Mode_Mem:
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{
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Memory operand_right = cast( Memory, Byte[1] & Mask_Memory );
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length += 2;
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if ( operand_right == Add_Direct )
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{
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u16 address = EffAddr.Disp;
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str_operand = string_format( "[ %u ]", address );
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}
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else
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{
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str_operand = str_memory( operand_right );
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}
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}
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break;
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case Mode_Mem8:
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{
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Memory operand_right = cast( Memory, Byte[1] & Mask_Memory );
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length += 1;
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str_operand = string_format( "[ %s + %u ]", str_memory( operand_right), EffAddr.Disp.Low );
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}
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break;
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case Mode_Mem16:
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{
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length += 2;
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Memory operand_right = cast( Memory, Byte[1] & Mask_Memory );
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u16 address = EffAddr.Disp;
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str_operand = string_format( "[ %s + %u ]", str_memory( operand_right), address );
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}
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break;
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case Mode_Reg:
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str_operand = Register::meumonic( mode_operand_right_reg(), width );
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break;
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}
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}
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u8 dissassemble( zpl_string* result_out )
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{
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using namespace Field;
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using namespace Op;
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using namespace Register;
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u8 length = 1;
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zpl_string assembly = string_make( 32);
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Code code = get_opcode( Op::Mask );
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Direction dir = get_direction();
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char const* str_operand_left = nullptr;
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char const* str_operand_right = nullptr;
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const u8 code_low = Byte[0] & Op::Mask_Low;
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const u8 code_high = Byte[0] & Op::Mask_High;
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const u8 sig_imme = Byte[0] & Op::Mask_Imme;
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if ( get_opcode( Op::Mask_Low ) == mov_Im_R )
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{
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Width width = get_width( Mask_Width_Imme );
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Reg reg = cast(Reg, Byte[0] & Register::Mask_Right );
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u16 immediate = width == Width_Byte ?
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Imme.Data.Low : Imme.Data;
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str_operand_left = Register::meumonic( reg, width );
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str_operand_right = string_format( "%u", immediate );
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}
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else
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{
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switch ( code )
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{
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#pragma region mov
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case mov_RM_R:
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{
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length++;
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Width width = get_width( Mask_Width );
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str_operand_left = Register::meumonic( mode_operand_left_reg(), width );
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dissassemble_mode( str_operand_right, width, length );
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}
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break;
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case mov_Im_RM:
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{
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Width width = get_width( Mask_Width_Imme );
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Memory operand_left = cast( Memory, Byte[1] & Mask_Memory );
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u16 address = EffAddr.Disp;
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u16 immediate = width == Width_Byte ?
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EffAddr.Data.Low : EffAddr.Data;
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dissassemble_mode( str_operand_left, width, length );
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str_operand_right = string_format( "%u", immediate );
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}
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break;
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case mov_M_Acc:
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{
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Width width = get_width( Mask_Width );
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u16 address = width == Width_Byte ?
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Addr.Data.Low : Addr.Data;
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str_operand_left = Register::meumonic( Reg::AX, Width_Word );
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str_operand_right = string_format( "%u", address );
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}
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break;
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case mov_Acc_M:
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{
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Width width = get_width( Mask_Width );
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u16 address = width == Width_Byte ?
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Addr.Data.Low : Addr.Data;
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str_operand_right = string_format( "%u", address );
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str_operand_left = Register::meumonic( Reg::AX, Width_Word );
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}
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break;
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case mov_RM_SR:
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{
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}
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break;
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case mov_SR_RM:
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{
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}
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break;
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#pragma endregion mov
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}
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}
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assembly = string_format( assembly, 32, "\n%s %s, %s"
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// opcode operand_right, operand_left
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, Op::meumonic( code)
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, str_operand_right
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, str_operand_left
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);
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if ( result_out == nullptr )
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return length;
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if ( * result_out == nullptr )
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* result_out = string_make( zpl_kilobytes(1) );
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* result_out = string_append( * result_out, assembly );
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zpl_printf("\n\nAssembly: %s\n\n", assembly);
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return length;
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}
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};
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namespace Tests
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{
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void try_mock_instruction()
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{
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using namespace Field;
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using namespace Op;
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using namespace Register;
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Instruction
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mock; // mov CX, BX
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mock.Byte[0] = mov_RM_R | Dir_Src | Field::Width_Word;
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mock.Byte[1] = Field::Mode_Reg | offset_left_reg(BX) | CX;
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zpl_printf("\n\nAttempting Mock Instruction: mov CX, BX");
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print_nl();
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print_as_binary( & mock.Byte[0], 1, " " );
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print_as_binary( & mock.Byte[1], 1, " " );
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print_nl();
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zpl_string dissasembly = nullptr;
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mock.dissassemble( & dissasembly);
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}
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void try_blob_single_move()
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{
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zpl_printf("\n\nAttempting to read blob: listing_0037_single_register_mov");
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zpl_file_contents
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|
blob = zpl_file_read_contents( g_allocator, false, "tests/listing_0037_single_register_mov" );
|
|
|
|
if (blob.data == nullptr )
|
|
return;
|
|
|
|
u32 left = blob.size;
|
|
u8* data = cast( u8*, blob.data );
|
|
|
|
print_nl();
|
|
print_as_binary( data, left, " " );
|
|
print_nl();
|
|
|
|
zpl_string dissasembly = nullptr;
|
|
|
|
Instruction
|
|
instr;
|
|
instr.Byte[0] = data[0];
|
|
instr.Byte[1] = data[1];
|
|
instr.dissassemble( & dissasembly);
|
|
}
|
|
|
|
void try_blob_many_moves()
|
|
{
|
|
zpl_printf("\n\nAttempting to read blob: listing_0038_many_register_mov");
|
|
|
|
zpl_file_contents
|
|
blob = zpl_file_read_contents( g_allocator, false, "tests/listing_0038_many_register_mov" );
|
|
|
|
if (blob.data == nullptr )
|
|
return;
|
|
|
|
u32 left = blob.size;
|
|
u8* data = cast( u8*, blob.data );
|
|
|
|
print_nl();
|
|
print_as_binary( data, left, " " );
|
|
print_nl();
|
|
|
|
zpl_string dissasembly = string_make( "bits 16\n");
|
|
|
|
while ( left )
|
|
{
|
|
Instruction
|
|
instr;
|
|
instr.Byte[0] = data[0];
|
|
instr.Byte[1] = data[1];
|
|
instr.dissassemble( & dissasembly);
|
|
|
|
data += 2;
|
|
left -= 2;
|
|
}
|
|
|
|
zpl_printf("\n\nDissassemlby:\n%s", dissasembly);
|
|
dissasembly = zpl_string_append_fmt( dissasembly, "\n" );
|
|
|
|
zpl_printf("\n\nSaving to file");
|
|
zpl_file_write_contents("tests/listing_0038_many_register_mov.out.asm"
|
|
, dissasembly
|
|
, zpl_string_length(dissasembly)
|
|
, nullptr
|
|
);
|
|
}
|
|
|
|
void try_blob_more_moves()
|
|
{
|
|
zpl_printf("\n\nAttempting to read blob: listing_0039_more_movs");
|
|
|
|
zpl_file_contents
|
|
blob = zpl_file_read_contents( g_allocator, false, "tests/listing_0039_more_movs" );
|
|
|
|
if (blob.data == nullptr )
|
|
return;
|
|
|
|
u32 left = blob.size;
|
|
u8* data = cast( u8*, blob.data );
|
|
|
|
print_nl();
|
|
print_as_binary( data, left, " " );
|
|
print_nl();
|
|
|
|
zpl_string dissasembly = string_make( "bits 16\n");
|
|
|
|
while ( left )
|
|
{
|
|
Instruction
|
|
instr;
|
|
instr.Ptr = data;
|
|
|
|
u8 length = instr.dissassemble( & dissasembly);
|
|
|
|
data += length;
|
|
left -= length;
|
|
}
|
|
|
|
zpl_printf("\n\nDissassemlby:\n%s", dissasembly);
|
|
dissasembly = zpl_string_append_fmt( dissasembly, "\n" );
|
|
|
|
zpl_printf("\n\nSaving to file");
|
|
zpl_file_write_contents("tests/listing_0039_more_movs.asm.out.asm"
|
|
, dissasembly
|
|
, zpl_string_length(dissasembly)
|
|
, nullptr
|
|
);
|
|
}
|
|
}
|
|
|
|
|
|
int main()
|
|
{
|
|
zpl_printf("sim 8086!");
|
|
|
|
setup();
|
|
|
|
f64 start = zpl_time_rel();
|
|
|
|
// Tests::try_blob_single_move();
|
|
// Tests::try_blob_many_moves();
|
|
Tests::try_blob_more_moves();
|
|
|
|
f64 end = zpl_time_rel();
|
|
f64 ms = (end - start) * 100;
|
|
|
|
printf("\n\nElapsed Time: %lf ms", ms);
|
|
printf("\n\n");
|
|
|
|
cleanup();
|
|
|
|
return 0;
|
|
}
|