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ed
2026-09-09 16:04:16 -04:00
parent 21334b48d8
commit 8912f3e0e9
6 changed files with 284 additions and 477 deletions
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code/8086/decoder.c
+20 -20
View File
@@ -35,7 +35,7 @@ typedef Struct_(X8616_DecodePlex) {
U1 plan_idx;
X8616_DecodePlan* plan;
U1 opcode;
U1 header;
U1 post_opcode;
U1 mod_rm;
@@ -82,8 +82,8 @@ typedef Struct_(X8616_DecodePlex) {
FI_ U2 x8616_decode_u2(U1_R bytes) { return C_(U2, bytes[0] | u2_(bytes[1] << 8)); }
internal X8616_OpcodePrefix
x8616_decode_opcode(X8616_DecodePlan const* plan, U1 opcode)
internal X8616_Opcode
x8616_decode_opcode(X8616_DecodePlan const* plan, U1 header)
{
U1 field_mask = 0;
if (plan->flags & x8616_plan_has_d) field_mask |= x8616_field_mask(plan->d_shift, X8616_OPCODE_BIT_WIDTH);
@@ -97,9 +97,9 @@ x8616_decode_opcode(X8616_DecodePlan const* plan, U1 opcode)
if (plan->flags & x8616_plan_has_cc) field_mask |= x8616_field_mask(plan->cc_shift, X8616_OPCODE_CC_WIDTH);
if (plan->flags & x8616_plan_has_pair) field_mask |= x8616_field_mask(plan->pair_shift, X8616_OPCODE_PAIR_WIDTH);
if (field_mask == 0) return 0;
U1 stem_mask = u1_(~field_mask);
if (stem_mask == 0) return 0;
return C_(X8616_OpcodePrefix, (opcode & stem_mask) >> count_trailing_zeros_u4(stem_mask));
U1 opcode_mask = u1_(~field_mask);
if (opcode_mask == 0) return 0;
return C_(X8616_Opcode, (header & opcode_mask) >> count_trailing_zeros_u4(opcode_mask));
}
internal void
@@ -141,8 +141,8 @@ x8616_decode_one_plex(X8616_DecodePlex* plex)
for (U1 idx = 0; idx < plex->body_available; ++ idx) plex->body[idx] = plex->source[prefix_at + idx];
plex->opcode = plex->body[0];
plex->dispatch = x8616_decode_dispatch[plex->opcode];
plex->header = plex->body[0];
plex->dispatch = x8616_decode_dispatch[plex->header];
if (body_source_size == 0) {
plex->classification_truncated = 1;
@@ -192,7 +192,7 @@ x8616_decode_one_plex(X8616_DecodePlex* plex)
, plex->source_offset + prefix_at
, 1
, 0
, plex->opcode
, plex->header
);
}
}
@@ -256,13 +256,13 @@ x8616_decode_one_plex(X8616_DecodePlex* plex)
}
X8616_DecodePlan_R plan = plex->plan;
plex->d = C_(X8616_Direction, x8616_bit_field_extract(plex->opcode, (X8616_BitField){ plan->d_shift, X8616_OPCODE_BIT_WIDTH }));
plex->w = C_(X8616_Width, x8616_bit_field_extract(plex->opcode, (X8616_BitField){ plan->w_shift, X8616_OPCODE_BIT_WIDTH }));
plex->s = C_(X8616_Sign, x8616_bit_field_extract(plex->opcode, (X8616_BitField){ plan->s_shift, X8616_OPCODE_BIT_WIDTH }));
plex->v = C_(X8616_VariableShift, x8616_bit_field_extract(plex->opcode, (X8616_BitField){ plan->v_shift, X8616_OPCODE_BIT_WIDTH }));
plex->z = C_(X8616_Repeat, x8616_bit_field_extract(plex->opcode, (X8616_BitField){ plan->z_shift, X8616_OPCODE_BIT_WIDTH }));
plex->reg_opcode.r16 = C_(X8616_Reg16, x8616_bit_field_extract(plex->opcode, (X8616_BitField){ plan->reg_shift, X8616_OPCODE_REG_REG_WIDTH }));
plex->sr_opcode = C_(X8616_Segment, x8616_bit_field_extract(plex->opcode, (X8616_BitField){ plan->sr_shift, X8616_OPCODE_SR_WIDTH }));
plex->d = C_(X8616_Direction, x8616_bit_field_extract(plex->header, (X8616_BitField){ plan->d_shift, X8616_OPCODE_BIT_WIDTH }));
plex->w = C_(X8616_Width, x8616_bit_field_extract(plex->header, (X8616_BitField){ plan->w_shift, X8616_OPCODE_BIT_WIDTH }));
plex->s = C_(X8616_Sign, x8616_bit_field_extract(plex->header, (X8616_BitField){ plan->s_shift, X8616_OPCODE_BIT_WIDTH }));
plex->v = C_(X8616_VariableShift, x8616_bit_field_extract(plex->header, (X8616_BitField){ plan->v_shift, X8616_OPCODE_BIT_WIDTH }));
plex->z = C_(X8616_Repeat, x8616_bit_field_extract(plex->header, (X8616_BitField){ plan->z_shift, X8616_OPCODE_BIT_WIDTH }));
plex->reg_opcode.r16 = C_(X8616_Reg16, x8616_bit_field_extract(plex->header, (X8616_BitField){ plan->reg_shift, X8616_OPCODE_REG_REG_WIDTH }));
plex->sr_opcode = C_(X8616_Segment, x8616_bit_field_extract(plex->header, (X8616_BitField){ plan->sr_shift, X8616_OPCODE_SR_WIDTH }));
plex->width = plan->width;
if (plex->width == x8616_width_dynamic && (plan->flags & x8616_plan_has_w))
@@ -285,10 +285,10 @@ x8616_decode_one_plex(X8616_DecodePlex* plex)
}
if (plan->flags & x8616_plan_has_alu) {
plex->alu = C_(X8616_ALU, x8616_bit_field_extract(plex->opcode, (X8616_BitField){ plan->alu_shift, X8616_OPCODE_ALU_TTT_WIDTH }));
plex->alu = C_(X8616_ALU, x8616_bit_field_extract(plex->header, (X8616_BitField){ plan->alu_shift, X8616_OPCODE_ALU_TTT_WIDTH }));
}
if (plan->flags & x8616_plan_has_cc) {
plex->cc = C_(X8616_Condition, x8616_bit_field_extract(plex->opcode, (X8616_BitField){ plan->cc_shift, X8616_OPCODE_CC_WIDTH }));
plex->cc = C_(X8616_Condition, x8616_bit_field_extract(plex->header, (X8616_BitField){ plan->cc_shift, X8616_OPCODE_CC_WIDTH }));
}
plex->displacement_at = plex->body_at;
@@ -445,7 +445,7 @@ x8616_decode_one_plex(X8616_DecodePlex* plex)
else if (plan->digit_kind == x8616_digit_incdec) plex->instruction.op = x8616_op_from_incdec[digit];
}
if (plan->flags & x8616_plan_has_pair) {
U1 bit = x8616_bit_field_extract(plex->opcode, (X8616_BitField){ plan->pair_shift, X8616_OPCODE_PAIR_WIDTH });
U1 bit = x8616_bit_field_extract(plex->header, (X8616_BitField){ plan->pair_shift, X8616_OPCODE_PAIR_WIDTH });
if (plan->pair_kind == x8616_pair_incdec) plex->instruction.op = x8616_op_from_incdec[bit];
if (plan->pair_kind == x8616_pair_pushpop) plex->instruction.op = x8616_op_from_pushpop[bit];
}
@@ -454,7 +454,7 @@ x8616_decode_one_plex(X8616_DecodePlex* plex)
plex->instruction.width = plex->width;
plex->instruction.prefixes = plex->prefixes;
plex->instruction.operand_count = plan->operand_count;
plex->instruction.opcode = x8616_decode_opcode(plan, plex->opcode);
plex->instruction.opcode = x8616_decode_opcode(plan, plex->header);
plex->instruction.d = (plan->flags & x8616_plan_has_d) ? plex->d : x8616_d_rm_dst;
plex->instruction.w = (plan->flags & x8616_plan_has_w) ? plex->w : x8616_w_byte;
plex->instruction.has_mod_rm = (plan->flags & x8616_plan_has_modrm) != 0;
code/8086/decoder.h
+1 -1
View File
@@ -68,7 +68,7 @@ typedef Struct_(X8616_DecodedInstruction) {
X8616_WidthMode width;
X8616_DecodedPrefixes prefixes;
X8616_DecodedOperand operands[2]; U1 operand_count;
X8616_OpcodePrefix opcode;
X8616_Opcode opcode;
X8616_Direction d;
X8616_Width w;
X8616_ALU alu;
code/8086/decoder_table_generator.meta.c
+1 -1
View File
@@ -146,7 +146,7 @@ x8616_decode_gen_plan(X8616_Encoding_R encoding, U4 encoding_idx, X8616_InfoList
}
FI_ B4 x8616_decode_gen_encoding_matches_opcode(X8616_Encoding_R encoding, U1 opcode) {
return (opcode & encoding->opcode.mask) == encoding->opcode.bits;
return (opcode & encoding->header.mask) == encoding->header.bits;
}
FI_ B4 x8616_decode_gen_plan_matches_second(X8616_DecodePlan_R plan, U1 byte) {
code/8086/encoder.h
+61 -33
View File
@@ -3,6 +3,16 @@
# include "duffle/dsl.h"
#endif
/* Intel 8086 Family User's Manual, Oct 1979 (9800722-03) ch.4 p.4-18,
Figure 4-20, Table 4-11, Table 4-12.
Opcode = the identifying bits in Table 4-12 (width varies: 4, 5, 6, 7, or 8).
Not the first instruction byte.
Fields = d, w, s, v, z, reg, sr (Table 4-11). Packed into that same byte.
Header = byte 1 as stored: opcode bits sitting in position, field bits OR'd in.
BytePattern matches a header byte: .bits = opcode << field_width (fields zero),
.mask = bits of the header that are opcode. */
typedef Struct_(X8616_BytePattern) { U1 bits; U1 mask; };
typedef Struct_(X8616_BitField) { U1 shift; U1 width; };
@@ -20,7 +30,9 @@ typedef Struct_(X8616_OpcodeFields) {
};
#define x8616_field_mask(shift, width) u1_(((1u << (width)) - 1u) << (shift))
#define x8616_stem_mask(low_width) u1_(~((1u << (low_width)) - 1u))
#define x8616_header_opcode_mask(field_width) u1_(~((1u << (field_width)) - 1u))
#define x8616_opc(opcode, field_width) ((X8616_BytePattern){ u1_((opcode) << (field_width)), x8616_header_opcode_mask(field_width) })
#define x8616_opc_byte(opcode) x8616_opc((opcode), 0)
typedef Enum_(U1, X8616_Op) {
x8616_op_invalid = 0x00,
@@ -164,15 +176,16 @@ typedef Enum_(U1, X8616_PairKind) {
x8616_pair_pushpop = 0x2,
};
/* mod_rm (Optional): Fixed constraint on the ModR/M byte.
post_opcode (Optional): Fixed byte immediately following the opcode.
fields: Variable fields carried by the opcode byte. width == 0: field is absent.
/* header: Byte 1 match (opcode bits aligned, field bits masked). Not the opcode.
mod_rm: Optional constraint on the ModR/M byte.
post_opcode: Optional fixed byte immediately after byte 1 (AAM/AAD imm).
fields: Table 4-11 fields packed into byte 1. width == 0: field is absent.
operands: Operand order describes d == 0.
If d exists and decodes to 1, operands[0] and operands[1] are swapped.
width: Explicit width only when the encoding has no w field.
flags: Encoding metadata not represented by an explicit operand. */
typedef Struct_(X8616_Encoding) {
X8616_BytePattern opcode;
X8616_BytePattern header;
X8616_BytePattern mod_rm;
X8616_BytePattern post_opcode;
X8616_OpcodeFields fields;
@@ -248,6 +261,12 @@ typedef Enum_(U1, X8616_Segment) {
x8616_ds = 0b11,
};
/* Table 4-12 B(110) / B(111) beside SR. Not opcode, not the SR field. */
typedef Enum_(U1, X8616_SRLow) {
x8616_sr_low_push = 0b110,
x8616_sr_low_pop = 0b111,
};
typedef Enum_(U1, X8616_EA) {
x8616_ea_bx_si = 0b000,
x8616_ea_bx_di = 0b001,
@@ -353,9 +372,14 @@ RO_ global X8616_Op x8616_op_from_incdec[] = {
[x8616_dec] = x8616_op_dec,
};
typedef Enum_(U1, X8616_PushPop) {
x8616_pushpop_push = 0b0,
x8616_pushpop_pop = 0b1,
};
RO_ global X8616_Op x8616_op_from_pushpop[] = {
[0] = x8616_op_push,
[1] = x8616_op_pop,
[x8616_pushpop_push] = x8616_op_push,
[x8616_pushpop_pop] = x8616_op_pop,
};
typedef Enum_(U1, X8616_Condition) {
@@ -400,7 +424,10 @@ typedef Enum_(U1, X8616_Digit) {
x8616_digit_0 = 0b000,
};
typedef Enum_(U1, X8616_OpcodePrefix) {
/* Table 4-12 identifying bits. Width is however many bits Intel printed
before d/w/reg/cccc. Not a constructed header byte.
INC register = 01000, not 0x40. HLT = 11110100 (opcode fills byte 1). */
typedef Enum_(U1, X8616_Opcode) {
x8616_opcode_mov_rm_r = 0b100010,
x8616_opcode_mov_rm_i = 0b1100011,
x8616_opcode_mov_r_i = 0b1011,
@@ -434,10 +461,11 @@ typedef Enum_(U1, X8616_OpcodePrefix) {
x8616_opcode_stos = 0b1010101,
x8616_opcode_jcc = 0b0111,
};
typedef Enum_(U1, X8616_Opcode) {
x8616_opcode_group_ff = 0b11111111,
/* Table 4-12: B(000) SR B(110/111), B(001) SR B(110). Class bits only. */
x8616_opcode_sr_stack = 0b000,
x8616_opcode_sr_override = 0b001,
x8616_opcode_pop_rm = 0b10001111,
x8616_opcode_xlat = 0b11010111,
x8616_opcode_lea = 0b10001101,
@@ -487,8 +515,6 @@ typedef Enum_(U1, X8616_Opcode) {
x8616_opcode_hlt = 0b11110100,
x8616_opcode_wait = 0b10011011,
x8616_opcode_lock = 0b11110000,
x8616_opcode_nop = 0b10010000,
};
enum {
@@ -524,33 +550,33 @@ enum {
X8616_OPCODE_DW_W_SHIFT = 0,
X8616_OPCODE_DW_D_SHIFT = 1,
X8616_OPCODE_DW_PREFIX_SHIFT = X8616_OPCODE_DW_D_SHIFT + 1,
X8616_OPCODE_DW_PREFIX_MASK = x8616_stem_mask(X8616_OPCODE_DW_PREFIX_SHIFT),
X8616_OPCODE_DW_PREFIX_MASK = x8616_header_opcode_mask(X8616_OPCODE_DW_PREFIX_SHIFT),
// ... s w
X8616_OPCODE_SW_W_SHIFT = 0,
X8616_OPCODE_SW_S_SHIFT = 1,
X8616_OPCODE_SW_PREFIX_SHIFT = X8616_OPCODE_SW_S_SHIFT + 1,
X8616_OPCODE_SW_PREFIX_MASK = x8616_stem_mask(X8616_OPCODE_SW_PREFIX_SHIFT),
X8616_OPCODE_SW_PREFIX_MASK = x8616_header_opcode_mask(X8616_OPCODE_SW_PREFIX_SHIFT),
// ... v w
X8616_OPCODE_VW_W_SHIFT = 0,
X8616_OPCODE_VW_V_SHIFT = 1,
X8616_OPCODE_VW_PREFIX_SHIFT = X8616_OPCODE_VW_V_SHIFT + 1,
X8616_OPCODE_VW_PREFIX_MASK = x8616_stem_mask(X8616_OPCODE_VW_PREFIX_SHIFT),
X8616_OPCODE_VW_PREFIX_MASK = x8616_header_opcode_mask(X8616_OPCODE_VW_PREFIX_SHIFT),
// ... z
X8616_OPCODE_Z_Z_SHIFT = 0,
X8616_OPCODE_Z_PREFIX_SHIFT = X8616_OPCODE_Z_Z_SHIFT + 1,
X8616_OPCODE_Z_PREFIX_MASK = x8616_stem_mask(X8616_OPCODE_Z_PREFIX_SHIFT),
X8616_OPCODE_Z_PREFIX_MASK = x8616_header_opcode_mask(X8616_OPCODE_Z_PREFIX_SHIFT),
// ... w
X8616_OPCODE_W_W_SHIFT = 0,
X8616_OPCODE_W_PREFIX_SHIFT = X8616_OPCODE_W_W_SHIFT + 1,
X8616_OPCODE_W_PREFIX_MASK = x8616_stem_mask(X8616_OPCODE_W_PREFIX_SHIFT),
X8616_OPCODE_W_PREFIX_MASK = x8616_header_opcode_mask(X8616_OPCODE_W_PREFIX_SHIFT),
// ... reg
@@ -558,7 +584,7 @@ enum {
X8616_OPCODE_REG_REG_WIDTH = 3,
X8616_OPCODE_REG_REG_MASK = x8616_field_mask(X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH),
X8616_OPCODE_REG_PREFIX_SHIFT = X8616_OPCODE_REG_REG_SHIFT + X8616_OPCODE_REG_REG_WIDTH,
X8616_OPCODE_REG_PREFIX_MASK = x8616_stem_mask(X8616_OPCODE_REG_PREFIX_SHIFT),
X8616_OPCODE_REG_PREFIX_MASK = x8616_header_opcode_mask(X8616_OPCODE_REG_PREFIX_SHIFT),
// ... w reg
@@ -568,13 +594,13 @@ enum {
X8616_OPCODE_WREG_W_SHIFT = X8616_OPCODE_WREG_REG_SHIFT + X8616_OPCODE_WREG_REG_WIDTH,
X8616_OPCODE_WREG_W_MASK = x8616_field_mask(X8616_OPCODE_WREG_W_SHIFT, 1),
X8616_OPCODE_WREG_PREFIX_SHIFT = X8616_OPCODE_WREG_W_SHIFT + 1,
X8616_OPCODE_WREG_PREFIX_MASK = x8616_stem_mask(X8616_OPCODE_WREG_PREFIX_SHIFT),
X8616_OPCODE_WREG_PREFIX_MASK = x8616_header_opcode_mask(X8616_OPCODE_WREG_PREFIX_SHIFT),
// ... d 0 (bit 0 fixed, bit 1 = d, bits 7-2 = stem)
X8616_OPCODE_D0_D_SHIFT = 1,
X8616_OPCODE_D0_PREFIX_SHIFT = X8616_OPCODE_D0_D_SHIFT + 1,
X8616_OPCODE_D0_PREFIX_MASK = x8616_stem_mask(X8616_OPCODE_D0_PREFIX_SHIFT) | x8616_field_mask(0, 1),
X8616_OPCODE_D0_PREFIX_MASK = x8616_header_opcode_mask(X8616_OPCODE_D0_PREFIX_SHIFT) | x8616_field_mask(0, 1),
// class(3) | sr(2) | low(3)
@@ -586,9 +612,6 @@ enum {
X8616_OPCODE_SR_CLASS_WIDTH = 3,
X8616_OPCODE_SR_MASK = x8616_field_mask(X8616_OPCODE_SR_SHIFT, X8616_OPCODE_SR_WIDTH),
X8616_OPCODE_SR_PATTERN_MASK = u1_(~X8616_OPCODE_SR_MASK),
X8616_OPCODE_PUSH_SR_FIXED = (0b000 << X8616_OPCODE_SR_CLASS_SHIFT) | 0b110,
X8616_OPCODE_POP_SR_FIXED = (0b000 << X8616_OPCODE_SR_CLASS_SHIFT) | 0b111,
X8616_OPCODE_SEG_FIXED = (0b001 << X8616_OPCODE_SR_CLASS_SHIFT) | 0b110,
// 0111 cccc
@@ -610,6 +633,7 @@ enum {
X8616_OPCODE_PAIR_SHIFT = 3,
X8616_OPCODE_PAIR_WIDTH = 1,
X8616_OPCODE_PAIR_REG_PREFIX_SHIFT = X8616_OPCODE_PAIR_SHIFT + X8616_OPCODE_PAIR_WIDTH,
X8616_OPCODE_IO_CLASS = 0b1110,
X8616_OPCODE_IO_CLASS_SHIFT = 4,
};
@@ -670,10 +694,13 @@ FI_ U1 x8616_modrm_sr (U1 modrm) { return (
#define x8616_enc_vw(prefix,v,w) C_(U1, x8616_enc_vw_prefix(prefix) | x8616_enc_v(v) | x8616_enc_width(w))
#define x8616_enc_zp(prefix,z) C_(U1, x8616_enc_z_prefix(prefix) | x8616_enc_z(z))
#define x8616_enc_w(prefix,w) C_(U1, x8616_enc_w_prefix(prefix) | x8616_enc_width(w))
#define x8616_header_w(opcode,w) ((X8616_BytePattern){ x8616_enc_w((opcode), (w)), x8616_field_mask(0, 8) })
#define x8616_enc_reg(prefix,reg) C_(U1, x8616_enc_reg_prefix(prefix) | x8616_enc_opcode_reg(reg))
#define x8616_enc_wreg(prefix,w,reg) C_(U1, x8616_enc_wreg_prefix(prefix) | x8616_enc_wreg_width(w) | x8616_enc_opcode_reg(reg))
#define x8616_enc_d0(prefix,d) C_(U1, x8616_enc_d0_prefix(prefix) | x8616_enc_d(d))
#define x8616_enc_sr(fixed,sr) C_(U1, fixed | x8616_enc_opcode_sr(sr))
#define x8616_enc_sr(class,sr,low) C_(U1, ((class) << X8616_OPCODE_SR_CLASS_SHIFT) | x8616_enc_opcode_sr(sr) | (low))
#define x8616_header_sr(class,low) ((X8616_BytePattern){ u1_(((class) << X8616_OPCODE_SR_CLASS_SHIFT) | (low)), X8616_OPCODE_SR_PATTERN_MASK })
#define x8616_header_d0(opcode) ((X8616_BytePattern){ u1_((opcode) << X8616_OPCODE_D0_PREFIX_SHIFT), X8616_OPCODE_D0_PREFIX_MASK })
#define x8616_enc_jcc(cc) C_(U1, (x8616_opcode_jcc << X8616_OPCODE_CC_PREFIX_SHIFT) | x8616_enc_cc(cc))
#define x8616_enc_modrm(mod,reg,rm) C_(U1, x8616_enc_modrm_mod(mod) | x8616_enc_modrm_reg(reg) | x8616_enc_modrm_rm(rm))
#define x8616_enc_modrm_seg(mod,sr,rm) C_(U1, x8616_enc_modrm_mod(mod) | x8616_enc_modrm_sr(sr) | x8616_enc_modrm_rm(rm))
@@ -687,6 +714,7 @@ FI_ U1 x8616_modrm_sr (U1 modrm) { return (
#define x8616_enc_io(dx, out, w) C_(U1, (x8616_enc_io_stem(dx, out) << X8616_OPCODE_W_PREFIX_SHIFT) | x8616_enc_width(w))
#define x8616_enc_pair(bit) ((bit) << X8616_OPCODE_PAIR_SHIFT)
// Scalar / generic packets
#define x8616_emit_u2(value) u1_(u2_(value) >> 0), u1_(u2_(value) >> 8)
@@ -753,9 +781,9 @@ FI_ U1 x8616_modrm_sr (U1 modrm) { return (
#define x8616_push_r16(reg) x8616_enc_reg(x8616_opcode_push_reg,reg)
#define x8616_pop_r16(reg) x8616_enc_reg(x8616_opcode_pop_reg,reg)
#define x8616_push_seg(seg) x8616_enc_sr(X8616_OPCODE_PUSH_SR_FIXED,seg)
#define x8616_pop_seg(seg) x8616_enc_sr(X8616_OPCODE_POP_SR_FIXED,seg)
#define x8616_push_rm(mod,rm) x8616_emit_modrm(x8616_opcode_group_ff,mod,x8616_ff_push,rm)
#define x8616_push_seg(seg) x8616_enc_sr(x8616_opcode_sr_stack,seg,x8616_sr_low_push)
#define x8616_pop_seg(seg) x8616_enc_sr(x8616_opcode_sr_stack,seg,x8616_sr_low_pop)
#define x8616_push_rm(mod,rm) x8616_emit_modrm(x8616_enc_w(x8616_opcode_incdec_rm,x8616_w_word),mod,x8616_ff_push,rm)
#define x8616_pop_rm(mod,rm) x8616_emit_modrm(x8616_opcode_pop_rm,mod,x8616_digit_0,rm)
#define x8616_xchg_r8_r8(a,b) x8616_enc_w(x8616_opcode_xchg_rm_r,x8616_w_byte), x8616_enc_modrm(x8616_mod_reg,a,b)
@@ -887,20 +915,20 @@ FI_ U1 x8616_modrm_sr (U1 modrm) { return (
#define x8616_stosb() x8616_enc_w(x8616_opcode_stos,x8616_w_byte)
#define x8616_stosw() x8616_enc_w(x8616_opcode_stos,x8616_w_word)
#define x8616_lock_prefix() x8616_emit_op(x8616_opcode_lock)
#define x8616_segment_prefix(seg) x8616_enc_sr(X8616_OPCODE_SEG_FIXED,seg)
#define x8616_segment_prefix(seg) x8616_enc_sr(x8616_opcode_sr_override,seg,x8616_sr_low_push)
// Control transfer
#define x8616_call_rel16(rel) x8616_emit_op_i16(x8616_opcode_call_rel16,rel)
#define x8616_call_far(seg,off) x8616_emit_op_far(x8616_opcode_call_far,seg,off)
#define x8616_call_rm(mod,rm) x8616_emit_modrm(x8616_opcode_group_ff,mod,x8616_ff_call_near,rm)
#define x8616_call_far_rm(mod,rm) x8616_emit_modrm(x8616_opcode_group_ff,mod,x8616_ff_call_far,rm)
#define x8616_call_rm(mod,rm) x8616_emit_modrm(x8616_enc_w(x8616_opcode_incdec_rm,x8616_w_word),mod,x8616_ff_call_near,rm)
#define x8616_call_far_rm(mod,rm) x8616_emit_modrm(x8616_enc_w(x8616_opcode_incdec_rm,x8616_w_word),mod,x8616_ff_call_far,rm)
#define x8616_jmp_rel16(rel) x8616_emit_op_i16(x8616_opcode_jmp_rel16,rel)
#define x8616_jmp_rel8(rel) x8616_emit_op_i8(x8616_opcode_jmp_rel8,rel)
#define x8616_jmp_far(seg,off) x8616_emit_op_far(x8616_opcode_jmp_far,seg,off)
#define x8616_jmp_rm(mod,rm) x8616_emit_modrm(x8616_opcode_group_ff,mod,x8616_ff_jmp_near,rm)
#define x8616_jmp_far_rm(mod,rm) x8616_emit_modrm(x8616_opcode_group_ff,mod,x8616_ff_jmp_far,rm)
#define x8616_jmp_rm(mod,rm) x8616_emit_modrm(x8616_enc_w(x8616_opcode_incdec_rm,x8616_w_word),mod,x8616_ff_jmp_near,rm)
#define x8616_jmp_far_rm(mod,rm) x8616_emit_modrm(x8616_enc_w(x8616_opcode_incdec_rm,x8616_w_word),mod,x8616_ff_jmp_far,rm)
#define x8616_ret() x8616_emit_op(x8616_opcode_ret)
#define x8616_ret_i(bytes) x8616_emit_op_i16(x8616_opcode_ret_i,bytes)
code/8086/encoder_table.h
+129 -352
View File
@@ -9,7 +9,8 @@
// Part 1 target: the instruction cross-section exercised by Computer Enhance listing 0042.
// Later Part 1 simulation listings use a subset of this table.
//
// Fixed opcode bits are kept in binary/signature form;
// Table 4-12: .header is byte 1 (opcode bits aligned, fields masked).
// Opcode enums are the identifying bits, not that byte.
// ModR/M /digit selectors use their encoded enumeration values.
// =========================================================================================
@@ -18,10 +19,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
// MOV---------------------------------------------------------------------
/* MOV: 100010 d w | mod reg r/m */ {
.opcode = {
.bits = x8616_opcode_mov_rm_r << X8616_OPCODE_DW_PREFIX_SHIFT,
.mask = X8616_OPCODE_DW_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_mov_rm_r, X8616_OPCODE_DW_PREFIX_SHIFT),
.fields = {
.d = { X8616_OPCODE_DW_D_SHIFT, 1 },
.w = { X8616_OPCODE_DW_W_SHIFT, 1 },
@@ -31,10 +29,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MOV imm -> r/m: 1100011 w | mod 000 r/m */ {
.opcode = {
.bits = x8616_opcode_mov_rm_i << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_mov_rm_i, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_digit_0 << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -47,10 +42,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MOV imm -> reg: 1011 w reg */ {
.opcode = {
.bits = x8616_opcode_mov_r_i << X8616_OPCODE_WREG_PREFIX_SHIFT,
.mask = X8616_OPCODE_WREG_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_mov_r_i, X8616_OPCODE_WREG_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_WREG_W_SHIFT, 1 },
.reg = { X8616_OPCODE_WREG_REG_SHIFT, X8616_OPCODE_WREG_REG_WIDTH },
@@ -60,10 +52,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MOV accumulator <-> direct memory: 101000 d w */ {
.opcode = {
.bits = x8616_opcode_mov_acc_mem << X8616_OPCODE_DW_PREFIX_SHIFT,
.mask = X8616_OPCODE_DW_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_mov_acc_mem, X8616_OPCODE_DW_PREFIX_SHIFT),
.fields = {
.d = { X8616_OPCODE_DW_D_SHIFT, 1 },
.w = { X8616_OPCODE_DW_W_SHIFT, 1 },
@@ -73,10 +62,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MOV segment <-> r/m: 100011 d 0 | mod 0 sr r/m */ {
.opcode = {
.bits = x8616_opcode_mov_seg_rm << X8616_OPCODE_D0_PREFIX_SHIFT,
.mask = X8616_OPCODE_D0_PREFIX_MASK,
},
.header = x8616_header_d0(x8616_opcode_mov_seg_rm),
.mod_rm = {
.bits = 0,
.mask = X8616_MODRM_SEG_FIXED_MASK,
@@ -91,40 +77,42 @@ RO_ global X8616_Encoding x8616_encodings[] =
// Stack / exchange--------------------------------------------------------
/* PUSH r/m16: 11111111 | mod 110 r/m */ {
.opcode = {
.bits = x8616_opcode_group_ff,
.mask = X8616_OPCODE_MASK,
},
/* PUSH r/m16: 1111111 w=1 | mod 110 r/m */ {
.header = x8616_header_w(x8616_opcode_incdec_rm, x8616_w_word),
.mod_rm = {
.bits = x8616_ff_push << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
},
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
.operands = { x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_push,
},
/* PUSH/POP reg16: 0101 pair reg */ {
.opcode = {
.bits = 0b0101 << 4,
.mask = x8616_stem_mask(4),
},
/* PUSH reg16: 01010 reg */ {
.header = x8616_opc(x8616_opcode_push_reg, X8616_OPCODE_REG_PREFIX_SHIFT),
.fields = {
.pair = { X8616_OPCODE_PAIR_SHIFT, X8616_OPCODE_PAIR_WIDTH },
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
},
.operands = { x8616_operand_reg_opcode },
.width = x8616_width_word,
.pair_kind = x8616_pair_pushpop,
.op = x8616_op_invalid,
.op = x8616_op_push,
},
/* POP reg16: 01011 reg */ {
.header = x8616_opc(x8616_opcode_pop_reg, X8616_OPCODE_REG_PREFIX_SHIFT),
.fields = {
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
},
.operands = { x8616_operand_reg_opcode },
.width = x8616_width_word,
.op = x8616_op_pop,
},
/* PUSH segment: 000 sr 110 */ {
.opcode = {
.bits = X8616_OPCODE_PUSH_SR_FIXED,
.mask = X8616_OPCODE_SR_PATTERN_MASK,
},
.header = x8616_header_sr(x8616_opcode_sr_stack, x8616_sr_low_push),
.fields = {
.sr = { X8616_OPCODE_SR_SHIFT, X8616_OPCODE_SR_WIDTH },
},
@@ -134,10 +122,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* POP r/m16: 10001111 | mod 000 r/m */ {
.opcode = {
.bits = x8616_opcode_pop_rm,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_pop_rm),
.mod_rm = {
.bits = x8616_digit_0 << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -150,10 +135,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
/* POP segment: 000 sr 111 */ {
.opcode = {
.bits = X8616_OPCODE_POP_SR_FIXED,
.mask = X8616_OPCODE_SR_PATTERN_MASK,
},
.header = x8616_header_sr(x8616_opcode_sr_stack, x8616_sr_low_pop),
.fields = {
.sr = { X8616_OPCODE_SR_SHIFT, X8616_OPCODE_SR_WIDTH },
},
@@ -163,10 +145,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* XCHG r/m,reg: 1000011 w | mod reg r/m */ {
.opcode = {
.bits = x8616_opcode_xchg_rm_r << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_xchg_rm_r, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -175,10 +154,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* XCHG AX,reg16: 10010 reg (also encodes NOP at reg=AX) */ {
.opcode = {
.bits = x8616_opcode_xchg_ax_reg << X8616_OPCODE_REG_PREFIX_SHIFT,
.mask = X8616_OPCODE_REG_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_xchg_ax_reg, X8616_OPCODE_REG_PREFIX_SHIFT),
.fields = {
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
},
@@ -190,10 +166,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
// I/O / address / flags---------------------------------------------------
/* IN acc,imm8: 1110 0 10 w */ {
.opcode = {
.bits = x8616_enc_io_stem(0, 0) << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_in_i, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -202,10 +175,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* IN acc,DX: 1110 1 10 w */ {
.opcode = {
.bits = x8616_enc_io_stem(1, 0) << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_in_dx, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -214,10 +184,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* OUT imm8,acc: 1110 0 11 w */ {
.opcode = {
.bits = x8616_enc_io_stem(0, 1) << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_out_i, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -226,10 +193,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* OUT DX,acc: 1110 1 11 w */ {
.opcode = {
.bits = x8616_enc_io_stem(1, 1) << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_out_dx, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -238,72 +202,48 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* XLAT */ {
.opcode = {
.bits = x8616_opcode_xlat,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_xlat),
.op = x8616_op_xlat,
},
/* LEA: mod reg r/m */ {
.opcode = {
.bits = x8616_opcode_lea,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_lea),
.operands = { x8616_operand_reg_modrm, x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_lea,
},
/* LDS: mod reg r/m */ {
.opcode = {
.bits = x8616_opcode_lds,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_lds),
.operands = { x8616_operand_reg_modrm, x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_lds,
},
/* LES: mod reg r/m */ {
.opcode = {
.bits = x8616_opcode_les,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_les),
.operands = { x8616_operand_reg_modrm, x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_les,
},
/* LAHF */ {
.opcode = {
.bits = x8616_opcode_lahf,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_lahf),
.op = x8616_op_lahf,
},
/* SAHF */ {
.opcode = {
.bits = x8616_opcode_sahf,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_sahf),
.op = x8616_op_sahf,
},
/* PUSHF */ {
.opcode = {
.bits = x8616_opcode_pushf,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_pushf),
.op = x8616_op_pushf,
},
/* POPF */ {
.opcode = {
.bits = x8616_opcode_popf,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_popf),
.op = x8616_op_popf,
},
@@ -311,7 +251,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
// 00 ttt 0 d w | 00 ttt 10 w | 100000 s w /ttt
/* ALU r/m,reg: 00 ttt 0 d w */ {
.opcode = {
.header = {
.bits = x8616_enc_alu_class(),
.mask = x8616_field_mask(X8616_OPCODE_ALU_CLASS_SHIFT, X8616_OPCODE_ALU_CLASS_WIDTH)
| x8616_field_mask(X8616_OPCODE_ALU_BIT2_SHIFT, 1),
@@ -327,7 +267,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
/* ALU acc,imm: 00 ttt 10 w */ {
.opcode = {
.header = {
.bits = x8616_enc_alu_class() | (X8616_OPCODE_ALU_ACC_FORM << X8616_OPCODE_ALU_ACC_FORM_SHIFT),
.mask = x8616_field_mask(X8616_OPCODE_ALU_CLASS_SHIFT, X8616_OPCODE_ALU_CLASS_WIDTH)
| x8616_field_mask(X8616_OPCODE_ALU_ACC_FORM_SHIFT, 2),
@@ -341,10 +281,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* ALU imm,r/m: 100000 s w /ttt */ {
.opcode = {
.bits = x8616_opcode_alu_rm_i << X8616_OPCODE_SW_PREFIX_SHIFT,
.mask = X8616_OPCODE_SW_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_alu_rm_i, X8616_OPCODE_SW_PREFIX_SHIFT),
.fields = {
.s = { X8616_OPCODE_SW_S_SHIFT, 1 },
.w = { X8616_OPCODE_SW_W_SHIFT, 1 },
@@ -358,10 +295,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
// INC / DEC / unary / adjust---------------------------------------------
/* INC r/m: 1111111 w /0 */ {
.opcode = {
.bits = x8616_opcode_incdec_rm << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_incdec_rm, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_inc << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -373,42 +307,38 @@ RO_ global X8616_Encoding x8616_encodings[] =
.op = x8616_op_inc,
},
/* INC/DEC reg16: 0100 pair reg */ {
.opcode = {
.bits = 0b0100 << 4,
.mask = x8616_stem_mask(4),
},
/* INC reg16: 01000 reg */ {
.header = x8616_opc(x8616_opcode_inc_reg, X8616_OPCODE_REG_PREFIX_SHIFT),
.fields = {
.pair = { X8616_OPCODE_PAIR_SHIFT, X8616_OPCODE_PAIR_WIDTH },
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
},
.operands = { x8616_operand_reg_opcode },
.width = x8616_width_word,
.pair_kind = x8616_pair_incdec,
.op = x8616_op_invalid,
.op = x8616_op_inc,
},
/* DEC reg16: 01001 reg */ {
.header = x8616_opc(x8616_opcode_dec_reg, X8616_OPCODE_REG_PREFIX_SHIFT),
.fields = {
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
},
.operands = { x8616_operand_reg_opcode },
.width = x8616_width_word,
.op = x8616_op_dec,
},
/* AAA */ {
.opcode = {
.bits = x8616_opcode_aaa,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_aaa),
.op = x8616_op_aaa,
},
/* DAA */ {
.opcode = {
.bits = x8616_opcode_daa,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_daa),
.op = x8616_op_daa,
},
/* DEC r/m: 1111111 w /1 */ {
.opcode = {
.bits = x8616_opcode_incdec_rm << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_incdec_rm, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_dec << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -423,10 +353,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
/* NEG r/m: 1111011 w /neg */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_neg << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -439,10 +366,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MUL r/m: 1111011 w /mul */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_mul << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -455,10 +379,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* IMUL r/m: 1111011 w /imul */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_imul << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -471,10 +392,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* DIV r/m: 1111011 w /div */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_div << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -487,10 +405,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* IDIV r/m: 1111011 w /idiv */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_idiv << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -503,10 +418,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* NOT r/m: 1111011 w /not */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_not << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -519,26 +431,17 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* AAS */ {
.opcode = {
.bits = x8616_opcode_aas,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_aas),
.op = x8616_op_aas,
},
/* DAS */ {
.opcode = {
.bits = x8616_opcode_das,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_das),
.op = x8616_op_das,
},
/* AAM: 11010100 00001010 */ {
.opcode = {
.bits = x8616_opcode_aam,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_aam),
.post_opcode = {
.bits = X8616_POST_OPCODE_AAM_AAD,
.mask = X8616_OPCODE_MASK,
@@ -547,10 +450,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* AAD: 11010101 00001010 */ {
.opcode = {
.bits = x8616_opcode_aad,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_aad),
.post_opcode = {
.bits = X8616_POST_OPCODE_AAM_AAD,
.mask = X8616_OPCODE_MASK,
@@ -559,28 +459,19 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* CBW */ {
.opcode = {
.bits = x8616_opcode_cbw,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_cbw),
.op = x8616_op_cbw,
},
/* CWD */ {
.opcode = {
.bits = x8616_opcode_cwd,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_cwd),
.op = x8616_op_cwd,
},
// Shift / rotate / TEST---------------------------------------------------
/* SHIFT/ROTATE r/m,1|CL: 110100 v w /ttt */ {
.opcode = {
.bits = x8616_opcode_shift_rm << X8616_OPCODE_VW_PREFIX_SHIFT,
.mask = X8616_OPCODE_VW_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_shift_rm, X8616_OPCODE_VW_PREFIX_SHIFT),
.fields = {
.v = { X8616_OPCODE_VW_V_SHIFT, 1 },
.w = { X8616_OPCODE_VW_W_SHIFT, 1 },
@@ -592,10 +483,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
/* TEST r/m,reg: 1000010 w */ {
.opcode = {
.bits = x8616_opcode_test_rm_r << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_test_rm_r, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -604,10 +492,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* TEST r/m,imm: 1111011 w /0 */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_test << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -620,10 +505,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* TEST accumulator,imm: 1010100 w */ {
.opcode = {
.bits = x8616_opcode_test_acc_i << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_test_acc_i, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -634,10 +516,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
// String / prefixes-------------------------------------------------------
/* REP/REPNE prefix: 1111001 z */ {
.opcode = {
.bits = x8616_opcode_rep << X8616_OPCODE_Z_PREFIX_SHIFT,
.mask = X8616_OPCODE_Z_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_rep, X8616_OPCODE_Z_PREFIX_SHIFT),
.fields = {
.z = { X8616_OPCODE_Z_Z_SHIFT, 1 },
},
@@ -646,10 +525,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MOVS: ... w */ {
.opcode = {
.bits = x8616_opcode_movs << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_movs, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -657,10 +533,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* CMPS: ... w */ {
.opcode = {
.bits = x8616_opcode_cmps << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_cmps, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -668,10 +541,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* SCAS: ... w */ {
.opcode = {
.bits = x8616_opcode_scas << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_scas, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -679,10 +549,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* LODS: ... w */ {
.opcode = {
.bits = x8616_opcode_lods << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_lods, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -690,10 +557,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* STOS: ... w */ {
.opcode = {
.bits = x8616_opcode_stos << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_stos, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -701,19 +565,13 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* LOCK prefix */ {
.opcode = {
.bits = x8616_opcode_lock,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_lock),
.flags = x8616_encoding_prefix,
.op = x8616_op_lock,
},
/* Segment override: 001 sr 110 */ {
.opcode = {
.bits = X8616_OPCODE_SEG_FIXED,
.mask = X8616_OPCODE_SR_PATTERN_MASK,
},
.header = x8616_header_sr(x8616_opcode_sr_override, x8616_sr_low_push),
.fields = {
.sr = { X8616_OPCODE_SR_SHIFT, X8616_OPCODE_SR_WIDTH },
},
@@ -724,47 +582,41 @@ RO_ global X8616_Encoding x8616_encodings[] =
// Control transfer--------------------------------------------------------
/* CALL rel16 */ {
.opcode = {
.bits = x8616_opcode_call_rel16,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_call_rel16),
.operands = { x8616_operand_rel16 },
.op = x8616_op_call,
},
/* CALL r/m16: FF /2 */ {
.opcode = {
.bits = x8616_opcode_group_ff,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_header_w(x8616_opcode_incdec_rm, x8616_w_word),
.mod_rm = {
.bits = x8616_ff_call_near << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
},
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
.operands = { x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_call,
},
/* CALL far ptr16:16 */ {
.opcode = {
.bits = x8616_opcode_call_far,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_call_far),
.operands = { x8616_operand_far_ptr },
.flags = x8616_encoding_far,
.op = x8616_op_call,
},
/* CALL far r/m16: FF /3 */ {
.opcode = {
.bits = x8616_opcode_group_ff,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_header_w(x8616_opcode_incdec_rm, x8616_w_word),
.mod_rm = {
.bits = x8616_ff_call_far << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
},
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
.operands = { x8616_operand_rm },
.width = x8616_width_word,
.flags = x8616_encoding_far,
@@ -772,56 +624,47 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* JMP rel16 */ {
.opcode = {
.bits = x8616_opcode_jmp_rel16,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_jmp_rel16),
.operands = { x8616_operand_rel16 },
.op = x8616_op_jmp,
},
/* JMP rel8 */ {
.opcode = {
.bits = x8616_opcode_jmp_rel8,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_jmp_rel8),
.operands = { x8616_operand_rel8 },
.op = x8616_op_jmp,
},
/* JMP r/m16: FF /4 */ {
.opcode = {
.bits = x8616_opcode_group_ff,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_header_w(x8616_opcode_incdec_rm, x8616_w_word),
.mod_rm = {
.bits = x8616_ff_jmp_near << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
},
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
.operands = { x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_jmp,
},
/* JMP far ptr16:16 */ {
.opcode = {
.bits = x8616_opcode_jmp_far,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_jmp_far),
.operands = { x8616_operand_far_ptr },
.flags = x8616_encoding_far,
.op = x8616_op_jmp,
},
/* JMP far r/m16: FF /5 */ {
.opcode = {
.bits = x8616_opcode_group_ff,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_header_w(x8616_opcode_incdec_rm, x8616_w_word),
.mod_rm = {
.bits = x8616_ff_jmp_far << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
},
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
.operands = { x8616_operand_rm },
.width = x8616_width_word,
.flags = x8616_encoding_far,
@@ -829,44 +672,29 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* RET */ {
.opcode = {
.bits = x8616_opcode_ret,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_ret),
.op = x8616_op_ret,
},
/* RET imm16 */ {
.opcode = {
.bits = x8616_opcode_ret_i,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_ret_i),
.operands = { x8616_operand_imm16 },
.op = x8616_op_ret,
},
/* RETF */ {
.opcode = {
.bits = x8616_opcode_retf,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_retf),
.op = x8616_op_retf,
},
/* RETF imm16 */ {
.opcode = {
.bits = x8616_opcode_retf_i,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_retf_i),
.operands = { x8616_operand_imm16 },
.op = x8616_op_retf,
},
/* Jcc rel8: 0111 cccc */ {
.opcode = {
.bits = x8616_opcode_jcc << X8616_OPCODE_CC_PREFIX_SHIFT,
.mask = x8616_stem_mask(X8616_OPCODE_CC_PREFIX_SHIFT),
},
.header = x8616_opc(x8616_opcode_jcc, X8616_OPCODE_CC_PREFIX_SHIFT),
.fields = {
.cc = { X8616_OPCODE_CC_SHIFT, X8616_OPCODE_CC_WIDTH },
},
@@ -876,37 +704,25 @@ RO_ global X8616_Encoding x8616_encodings[] =
/* LOOPNZ rel8 */ {
.opcode = {
.bits = x8616_opcode_loopnz,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_loopnz),
.operands = { x8616_operand_rel8 },
.op = x8616_op_loopnz,
},
/* LOOPZ rel8 */ {
.opcode = {
.bits = x8616_opcode_loopz,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_loopz),
.operands = { x8616_operand_rel8 },
.op = x8616_op_loopz,
},
/* LOOP rel8 */ {
.opcode = {
.bits = x8616_opcode_loop,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_loop),
.operands = { x8616_operand_rel8 },
.op = x8616_op_loop,
},
/* JCXZ rel8 */ {
.opcode = {
.bits = x8616_opcode_jcxz,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_jcxz),
.operands = { x8616_operand_rel8 },
.op = x8616_op_jcxz,
},
@@ -914,107 +730,68 @@ RO_ global X8616_Encoding x8616_encodings[] =
// Interrupt / machine control--------------------------------------------
/* INT imm8 */ {
.opcode = {
.bits = x8616_opcode_int,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_int),
.operands = { x8616_operand_imm8 },
.op = x8616_op_int,
},
/* INT3 */ {
.opcode = {
.bits = x8616_opcode_int3,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_int3),
.op = x8616_op_int3,
},
/* INTO */ {
.opcode = {
.bits = x8616_opcode_into,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_into),
.op = x8616_op_into,
},
/* IRET */ {
.opcode = {
.bits = x8616_opcode_iret,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_iret),
.op = x8616_op_iret,
},
/* CLC */ {
.opcode = {
.bits = x8616_opcode_clc,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_clc),
.op = x8616_op_clc,
},
/* CMC */ {
.opcode = {
.bits = x8616_opcode_cmc,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_cmc),
.op = x8616_op_cmc,
},
/* STC */ {
.opcode = {
.bits = x8616_opcode_stc,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_stc),
.op = x8616_op_stc,
},
/* CLD */ {
.opcode = {
.bits = x8616_opcode_cld,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_cld),
.op = x8616_op_cld,
},
/* STD */ {
.opcode = {
.bits = x8616_opcode_std,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_std),
.op = x8616_op_std,
},
/* CLI */ {
.opcode = {
.bits = x8616_opcode_cli,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_cli),
.op = x8616_op_cli,
},
/* STI */ {
.opcode = {
.bits = x8616_opcode_sti,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_sti),
.op = x8616_op_sti,
},
/* HLT */ {
.opcode = {
.bits = x8616_opcode_hlt,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_hlt),
.op = x8616_op_hlt,
},
/* WAIT */ {
.opcode = {
.bits = x8616_opcode_wait,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_wait),
.op = x8616_op_wait,
},
code/8086/gen/decoder_table.h
+65 -63
View File
@@ -4,7 +4,7 @@
# include "dsl.h"
#endif
RO_ global X8616_DecodePlan x8616_decode_plans[88] =
RO_ global X8616_DecodePlan x8616_decode_plans[90] =
{
{ 0x0000, 0x00, 0x00, 0x00, {0x00, 0x00}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x041a, 0x02, 0x00, 0x00, {0x01, 0x02}, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
@@ -12,8 +12,9 @@ RO_ global X8616_DecodePlan x8616_decode_plans[88] =
{ 0x0110, 0x02, 0x00, 0x00, {0x03, 0x07}, 2, 1, 0, 0, 3, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0018, 0x02, 0x00, 0x00, {0x06, 0x0a}, 2, 4, 0, 1, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x040a, 0x02, 0x00, 0x02, {0x01, 0x04}, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, {0x00, 0x20}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0402, 0x0b, 0x00, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x30, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x4100, 0x00, 0x00, 0x02, {0x03, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 3, 0, 2, },
{ 0x0412, 0x0b, 0x00, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x30, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0100, 0x0b, 0x00, 0x02, {0x03, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0100, 0x0c, 0x00, 0x02, {0x03, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0200, 0x0b, 0x00, 0x02, {0x05, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0402, 0x0c, 0x00, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0200, 0x0c, 0x00, 0x02, {0x05, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
@@ -35,7 +36,8 @@ RO_ global X8616_DecodePlan x8616_decode_plans[88] =
{ 0x1010, 0x00, 0x00, 0x00, {0x06, 0x07}, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 3, 0, 0, 0, 0, },
{ 0x0432, 0x00, 0x00, 0x00, {0x01, 0x07}, 2, 1, 0, 0, 0, 1, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 1, 0, },
{ 0x0412, 0x18, 0x00, 0x00, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x4100, 0x00, 0x00, 0x02, {0x03, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 3, 0, 1, },
{ 0x0100, 0x18, 0x00, 0x02, {0x03, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0100, 0x1b, 0x00, 0x02, {0x03, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0000, 0x19, 0x00, 0x00, {0x00, 0x00}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0000, 0x1a, 0x00, 0x00, {0x00, 0x00}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0412, 0x1b, 0x00, 0x00, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x08, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
@@ -64,14 +66,14 @@ RO_ global X8616_DecodePlan x8616_decode_plans[88] =
{ 0x0800, 0x5b, 0x02, 0x00, {0x00, 0x00}, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0a00, 0x5c, 0x02, 0x00, {0x00, 0x00}, 0, 0, 3, 0, 0, 0, 0, 0, 0, 3, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0000, 0x36, 0x00, 0x00, {0x0c, 0x00}, 1, 6, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0402, 0x36, 0x00, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x10, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0412, 0x36, 0x00, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x10, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0000, 0x36, 0x01, 0x00, {0x0d, 0x00}, 1, 7, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0402, 0x36, 0x01, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x18, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0412, 0x36, 0x01, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x18, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0000, 0x37, 0x00, 0x00, {0x0c, 0x00}, 1, 6, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0000, 0x37, 0x00, 0x00, {0x0b, 0x00}, 1, 5, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0402, 0x37, 0x00, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x20, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0412, 0x37, 0x00, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x20, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0000, 0x37, 0x01, 0x00, {0x0d, 0x00}, 1, 7, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0402, 0x37, 0x01, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x28, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0412, 0x37, 0x01, 0x02, {0x01, 0x00}, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x28, 0x38}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0000, 0x38, 0x00, 0x00, {0x00, 0x00}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0000, 0x38, 0x00, 0x00, {0x09, 0x00}, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
{ 0x0000, 0x39, 0x00, 0x00, {0x00, 0x00}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0x00, 0x00}, {0x00, 0x00}, 0, 0, 0, 0, 0, },
@@ -98,93 +100,93 @@ RO_ global X8616_DecodePlan x8616_decode_plans[88] =
RO_ global U2 x8616_decode_dispatch[256] =
{
0x0019, 0x0019, 0x0019, 0x0019, 0x001a, 0x001a, 0x0008, 0x000a, 0x0019, 0x0019, 0x0019, 0x0019, 0x001a, 0x001a, 0x0008, 0x000a,
0x0019, 0x0019, 0x0019, 0x0019, 0x001a, 0x001a, 0x0008, 0x000a, 0x0019, 0x0019, 0x0019, 0x0019, 0x001a, 0x001a, 0x0008, 0x000a,
0x0019, 0x0019, 0x0019, 0x0019, 0x001a, 0x001a, 0x0038, 0x001f, 0x0019, 0x0019, 0x0019, 0x0019, 0x001a, 0x001a, 0x0038, 0x0028,
0x0019, 0x0019, 0x0019, 0x0019, 0x001a, 0x001a, 0x0038, 0x001e, 0x0019, 0x0019, 0x0019, 0x0019, 0x001a, 0x001a, 0x0038, 0x0027,
0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d, 0x001d,
0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
0x001a, 0x001a, 0x001a, 0x001a, 0x001b, 0x001b, 0x0009, 0x000b, 0x001a, 0x001a, 0x001a, 0x001a, 0x001b, 0x001b, 0x0009, 0x000b,
0x001a, 0x001a, 0x001a, 0x001a, 0x001b, 0x001b, 0x0009, 0x000b, 0x001a, 0x001a, 0x001a, 0x001a, 0x001b, 0x001b, 0x0009, 0x000b,
0x001a, 0x001a, 0x001a, 0x001a, 0x001b, 0x001b, 0x003a, 0x0021, 0x001a, 0x001a, 0x001a, 0x001a, 0x001b, 0x001b, 0x003a, 0x002a,
0x001a, 0x001a, 0x001a, 0x001a, 0x001b, 0x001b, 0x003a, 0x0020, 0x001a, 0x001a, 0x001a, 0x001a, 0x001b, 0x001b, 0x003a, 0x0029,
0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001f, 0x001f, 0x001f, 0x001f, 0x001f, 0x001f, 0x001f, 0x001f,
0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046, 0x0046,
0x001b, 0x001b, 0x001b, 0x001b, 0x002e, 0x002e, 0x000b, 0x000b, 0x0001, 0x0001, 0x0001, 0x0001, 0x0005, 0x0012, 0x0005, 0x0009,
0x000c, 0x000c, 0x000c, 0x000c, 0x000c, 0x000c, 0x000c, 0x000c, 0x002b, 0x002c, 0x003b, 0x0057, 0x0017, 0x0018, 0x0016, 0x0015,
0x0004, 0x0004, 0x0004, 0x0004, 0x0032, 0x0032, 0x0033, 0x0033, 0x0030, 0x0030, 0x0036, 0x0036, 0x0035, 0x0035, 0x0034, 0x0034,
0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048, 0x0048,
0x001c, 0x001c, 0x001c, 0x001c, 0x0030, 0x0030, 0x000c, 0x000c, 0x0001, 0x0001, 0x0001, 0x0001, 0x0005, 0x0013, 0x0005, 0x000a,
0x000d, 0x000d, 0x000d, 0x000d, 0x000d, 0x000d, 0x000d, 0x000d, 0x002d, 0x002e, 0x003d, 0x0059, 0x0018, 0x0019, 0x0017, 0x0016,
0x0004, 0x0004, 0x0004, 0x0004, 0x0034, 0x0034, 0x0035, 0x0035, 0x0032, 0x0032, 0x0038, 0x0038, 0x0037, 0x0037, 0x0036, 0x0036,
0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
0x0000, 0x0000, 0x0043, 0x0042, 0x0014, 0x0013, 0x0002, 0x0002, 0x0000, 0x0000, 0x0045, 0x0044, 0x004c, 0x004b, 0x004d, 0x004e,
0x002d, 0x002d, 0x002d, 0x002d, 0x0029, 0x002a, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0047, 0x0048, 0x0049, 0x004a, 0x000d, 0x000d, 0x000f, 0x000f, 0x0039, 0x003d, 0x0040, 0x003e, 0x000e, 0x000e, 0x0010, 0x0010,
0x0037, 0x0000, 0x0031, 0x0031, 0x0056, 0x0050, 0x8000, 0x8100, 0x004f, 0x0051, 0x0054, 0x0055, 0x0052, 0x0053, 0x8200, 0x8300,
0x0000, 0x0000, 0x0045, 0x0044, 0x0015, 0x0014, 0x0002, 0x0002, 0x0000, 0x0000, 0x0047, 0x0046, 0x004e, 0x004d, 0x004f, 0x0050,
0x002f, 0x002f, 0x002f, 0x002f, 0x002b, 0x002c, 0x0000, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0049, 0x004a, 0x004b, 0x004c, 0x000e, 0x000e, 0x0010, 0x0010, 0x003b, 0x003f, 0x0042, 0x0040, 0x000f, 0x000f, 0x0011, 0x0011,
0x0039, 0x0000, 0x0033, 0x0033, 0x0058, 0x0052, 0x8000, 0x8100, 0x0051, 0x0053, 0x0056, 0x0057, 0x0054, 0x0055, 0x8200, 0x8300,
};
RO_ global U1 x8616_decode_aux[1024] =
{
0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21,
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21,
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27,
0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21,
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27,
0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21,
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27,
0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21,
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27,
0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21,
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27,
0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21,
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27,
0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21,
0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27,
0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23,
0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27, 0x27,
0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c,
0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41,
0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e,
0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43,
0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c,
0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41,
0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e,
0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43,
0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c,
0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41,
0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e,
0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43,
0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c,
0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41,
0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e, 0x3e,
0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43,
0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
enum {
X8616_DECODE_PLAN_COUNT = 88,
X8616_DECODE_PLAN_COUNT = 90,
X8616_DECODE_AUX_COUNT = 1024,
};