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ed
2026-09-09 16:04:16 -04:00
parent 21334b48d8
commit 8912f3e0e9
6 changed files with 284 additions and 477 deletions
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code/8086/encoder_table.h
+135 -358
View File
@@ -9,7 +9,8 @@
// Part 1 target: the instruction cross-section exercised by Computer Enhance listing 0042.
// Later Part 1 simulation listings use a subset of this table.
//
// Fixed opcode bits are kept in binary/signature form;
// Table 4-12: .header is byte 1 (opcode bits aligned, fields masked).
// Opcode enums are the identifying bits, not that byte.
// ModR/M /digit selectors use their encoded enumeration values.
// =========================================================================================
@@ -18,10 +19,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
// MOV---------------------------------------------------------------------
/* MOV: 100010 d w | mod reg r/m */ {
.opcode = {
.bits = x8616_opcode_mov_rm_r << X8616_OPCODE_DW_PREFIX_SHIFT,
.mask = X8616_OPCODE_DW_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_mov_rm_r, X8616_OPCODE_DW_PREFIX_SHIFT),
.fields = {
.d = { X8616_OPCODE_DW_D_SHIFT, 1 },
.w = { X8616_OPCODE_DW_W_SHIFT, 1 },
@@ -31,10 +29,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MOV imm -> r/m: 1100011 w | mod 000 r/m */ {
.opcode = {
.bits = x8616_opcode_mov_rm_i << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_mov_rm_i, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_digit_0 << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -47,10 +42,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MOV imm -> reg: 1011 w reg */ {
.opcode = {
.bits = x8616_opcode_mov_r_i << X8616_OPCODE_WREG_PREFIX_SHIFT,
.mask = X8616_OPCODE_WREG_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_mov_r_i, X8616_OPCODE_WREG_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_WREG_W_SHIFT, 1 },
.reg = { X8616_OPCODE_WREG_REG_SHIFT, X8616_OPCODE_WREG_REG_WIDTH },
@@ -60,10 +52,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MOV accumulator <-> direct memory: 101000 d w */ {
.opcode = {
.bits = x8616_opcode_mov_acc_mem << X8616_OPCODE_DW_PREFIX_SHIFT,
.mask = X8616_OPCODE_DW_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_mov_acc_mem, X8616_OPCODE_DW_PREFIX_SHIFT),
.fields = {
.d = { X8616_OPCODE_DW_D_SHIFT, 1 },
.w = { X8616_OPCODE_DW_W_SHIFT, 1 },
@@ -73,10 +62,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MOV segment <-> r/m: 100011 d 0 | mod 0 sr r/m */ {
.opcode = {
.bits = x8616_opcode_mov_seg_rm << X8616_OPCODE_D0_PREFIX_SHIFT,
.mask = X8616_OPCODE_D0_PREFIX_MASK,
},
.header = x8616_header_d0(x8616_opcode_mov_seg_rm),
.mod_rm = {
.bits = 0,
.mask = X8616_MODRM_SEG_FIXED_MASK,
@@ -91,40 +77,42 @@ RO_ global X8616_Encoding x8616_encodings[] =
// Stack / exchange--------------------------------------------------------
/* PUSH r/m16: 11111111 | mod 110 r/m */ {
.opcode = {
.bits = x8616_opcode_group_ff,
.mask = X8616_OPCODE_MASK,
},
/* PUSH r/m16: 1111111 w=1 | mod 110 r/m */ {
.header = x8616_header_w(x8616_opcode_incdec_rm, x8616_w_word),
.mod_rm = {
.bits = x8616_ff_push << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
},
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
.operands = { x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_push,
},
/* PUSH/POP reg16: 0101 pair reg */ {
.opcode = {
.bits = 0b0101 << 4,
.mask = x8616_stem_mask(4),
},
/* PUSH reg16: 01010 reg */ {
.header = x8616_opc(x8616_opcode_push_reg, X8616_OPCODE_REG_PREFIX_SHIFT),
.fields = {
.pair = { X8616_OPCODE_PAIR_SHIFT, X8616_OPCODE_PAIR_WIDTH },
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
},
.operands = { x8616_operand_reg_opcode },
.width = x8616_width_word,
.pair_kind = x8616_pair_pushpop,
.op = x8616_op_invalid,
.operands = { x8616_operand_reg_opcode },
.width = x8616_width_word,
.op = x8616_op_push,
},
/* POP reg16: 01011 reg */ {
.header = x8616_opc(x8616_opcode_pop_reg, X8616_OPCODE_REG_PREFIX_SHIFT),
.fields = {
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
},
.operands = { x8616_operand_reg_opcode },
.width = x8616_width_word,
.op = x8616_op_pop,
},
/* PUSH segment: 000 sr 110 */ {
.opcode = {
.bits = X8616_OPCODE_PUSH_SR_FIXED,
.mask = X8616_OPCODE_SR_PATTERN_MASK,
},
.header = x8616_header_sr(x8616_opcode_sr_stack, x8616_sr_low_push),
.fields = {
.sr = { X8616_OPCODE_SR_SHIFT, X8616_OPCODE_SR_WIDTH },
},
@@ -134,10 +122,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* POP r/m16: 10001111 | mod 000 r/m */ {
.opcode = {
.bits = x8616_opcode_pop_rm,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_pop_rm),
.mod_rm = {
.bits = x8616_digit_0 << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -150,10 +135,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
/* POP segment: 000 sr 111 */ {
.opcode = {
.bits = X8616_OPCODE_POP_SR_FIXED,
.mask = X8616_OPCODE_SR_PATTERN_MASK,
},
.header = x8616_header_sr(x8616_opcode_sr_stack, x8616_sr_low_pop),
.fields = {
.sr = { X8616_OPCODE_SR_SHIFT, X8616_OPCODE_SR_WIDTH },
},
@@ -163,10 +145,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* XCHG r/m,reg: 1000011 w | mod reg r/m */ {
.opcode = {
.bits = x8616_opcode_xchg_rm_r << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_xchg_rm_r, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -175,10 +154,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* XCHG AX,reg16: 10010 reg (also encodes NOP at reg=AX) */ {
.opcode = {
.bits = x8616_opcode_xchg_ax_reg << X8616_OPCODE_REG_PREFIX_SHIFT,
.mask = X8616_OPCODE_REG_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_xchg_ax_reg, X8616_OPCODE_REG_PREFIX_SHIFT),
.fields = {
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
},
@@ -190,10 +166,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
// I/O / address / flags---------------------------------------------------
/* IN acc,imm8: 1110 0 10 w */ {
.opcode = {
.bits = x8616_enc_io_stem(0, 0) << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_in_i, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -202,10 +175,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* IN acc,DX: 1110 1 10 w */ {
.opcode = {
.bits = x8616_enc_io_stem(1, 0) << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_in_dx, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -214,10 +184,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* OUT imm8,acc: 1110 0 11 w */ {
.opcode = {
.bits = x8616_enc_io_stem(0, 1) << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_out_i, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -226,10 +193,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* OUT DX,acc: 1110 1 11 w */ {
.opcode = {
.bits = x8616_enc_io_stem(1, 1) << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_out_dx, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -238,72 +202,48 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* XLAT */ {
.opcode = {
.bits = x8616_opcode_xlat,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_xlat),
.op = x8616_op_xlat,
},
/* LEA: mod reg r/m */ {
.opcode = {
.bits = x8616_opcode_lea,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_lea),
.operands = { x8616_operand_reg_modrm, x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_lea,
},
/* LDS: mod reg r/m */ {
.opcode = {
.bits = x8616_opcode_lds,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_lds),
.operands = { x8616_operand_reg_modrm, x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_lds,
},
/* LES: mod reg r/m */ {
.opcode = {
.bits = x8616_opcode_les,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_les),
.operands = { x8616_operand_reg_modrm, x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_les,
},
/* LAHF */ {
.opcode = {
.bits = x8616_opcode_lahf,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_lahf),
.op = x8616_op_lahf,
},
/* SAHF */ {
.opcode = {
.bits = x8616_opcode_sahf,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_sahf),
.op = x8616_op_sahf,
},
/* PUSHF */ {
.opcode = {
.bits = x8616_opcode_pushf,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_pushf),
.op = x8616_op_pushf,
},
/* POPF */ {
.opcode = {
.bits = x8616_opcode_popf,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_popf),
.op = x8616_op_popf,
},
@@ -311,7 +251,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
// 00 ttt 0 d w | 00 ttt 10 w | 100000 s w /ttt
/* ALU r/m,reg: 00 ttt 0 d w */ {
.opcode = {
.header = {
.bits = x8616_enc_alu_class(),
.mask = x8616_field_mask(X8616_OPCODE_ALU_CLASS_SHIFT, X8616_OPCODE_ALU_CLASS_WIDTH)
| x8616_field_mask(X8616_OPCODE_ALU_BIT2_SHIFT, 1),
@@ -327,7 +267,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
/* ALU acc,imm: 00 ttt 10 w */ {
.opcode = {
.header = {
.bits = x8616_enc_alu_class() | (X8616_OPCODE_ALU_ACC_FORM << X8616_OPCODE_ALU_ACC_FORM_SHIFT),
.mask = x8616_field_mask(X8616_OPCODE_ALU_CLASS_SHIFT, X8616_OPCODE_ALU_CLASS_WIDTH)
| x8616_field_mask(X8616_OPCODE_ALU_ACC_FORM_SHIFT, 2),
@@ -341,10 +281,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* ALU imm,r/m: 100000 s w /ttt */ {
.opcode = {
.bits = x8616_opcode_alu_rm_i << X8616_OPCODE_SW_PREFIX_SHIFT,
.mask = X8616_OPCODE_SW_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_alu_rm_i, X8616_OPCODE_SW_PREFIX_SHIFT),
.fields = {
.s = { X8616_OPCODE_SW_S_SHIFT, 1 },
.w = { X8616_OPCODE_SW_W_SHIFT, 1 },
@@ -358,10 +295,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
// INC / DEC / unary / adjust---------------------------------------------
/* INC r/m: 1111111 w /0 */ {
.opcode = {
.bits = x8616_opcode_incdec_rm << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_incdec_rm, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_inc << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -373,42 +307,38 @@ RO_ global X8616_Encoding x8616_encodings[] =
.op = x8616_op_inc,
},
/* INC/DEC reg16: 0100 pair reg */ {
.opcode = {
.bits = 0b0100 << 4,
.mask = x8616_stem_mask(4),
},
/* INC reg16: 01000 reg */ {
.header = x8616_opc(x8616_opcode_inc_reg, X8616_OPCODE_REG_PREFIX_SHIFT),
.fields = {
.pair = { X8616_OPCODE_PAIR_SHIFT, X8616_OPCODE_PAIR_WIDTH },
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
},
.operands = { x8616_operand_reg_opcode },
.width = x8616_width_word,
.pair_kind = x8616_pair_incdec,
.op = x8616_op_invalid,
.operands = { x8616_operand_reg_opcode },
.width = x8616_width_word,
.op = x8616_op_inc,
},
/* DEC reg16: 01001 reg */ {
.header = x8616_opc(x8616_opcode_dec_reg, X8616_OPCODE_REG_PREFIX_SHIFT),
.fields = {
.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
},
.operands = { x8616_operand_reg_opcode },
.width = x8616_width_word,
.op = x8616_op_dec,
},
/* AAA */ {
.opcode = {
.bits = x8616_opcode_aaa,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_aaa),
.op = x8616_op_aaa,
},
/* DAA */ {
.opcode = {
.bits = x8616_opcode_daa,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_daa),
.op = x8616_op_daa,
},
/* DEC r/m: 1111111 w /1 */ {
.opcode = {
.bits = x8616_opcode_incdec_rm << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_incdec_rm, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_dec << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -423,10 +353,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
/* NEG r/m: 1111011 w /neg */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_neg << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -439,10 +366,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MUL r/m: 1111011 w /mul */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_mul << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -455,10 +379,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* IMUL r/m: 1111011 w /imul */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_imul << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -471,10 +392,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* DIV r/m: 1111011 w /div */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_div << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -487,10 +405,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* IDIV r/m: 1111011 w /idiv */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_idiv << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -503,10 +418,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* NOT r/m: 1111011 w /not */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_not << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -519,26 +431,17 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* AAS */ {
.opcode = {
.bits = x8616_opcode_aas,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_aas),
.op = x8616_op_aas,
},
/* DAS */ {
.opcode = {
.bits = x8616_opcode_das,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_das),
.op = x8616_op_das,
},
/* AAM: 11010100 00001010 */ {
.opcode = {
.bits = x8616_opcode_aam,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_aam),
.post_opcode = {
.bits = X8616_POST_OPCODE_AAM_AAD,
.mask = X8616_OPCODE_MASK,
@@ -547,10 +450,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* AAD: 11010101 00001010 */ {
.opcode = {
.bits = x8616_opcode_aad,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_aad),
.post_opcode = {
.bits = X8616_POST_OPCODE_AAM_AAD,
.mask = X8616_OPCODE_MASK,
@@ -559,28 +459,19 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* CBW */ {
.opcode = {
.bits = x8616_opcode_cbw,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_cbw),
.op = x8616_op_cbw,
},
/* CWD */ {
.opcode = {
.bits = x8616_opcode_cwd,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_cwd),
.op = x8616_op_cwd,
},
// Shift / rotate / TEST---------------------------------------------------
/* SHIFT/ROTATE r/m,1|CL: 110100 v w /ttt */ {
.opcode = {
.bits = x8616_opcode_shift_rm << X8616_OPCODE_VW_PREFIX_SHIFT,
.mask = X8616_OPCODE_VW_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_shift_rm, X8616_OPCODE_VW_PREFIX_SHIFT),
.fields = {
.v = { X8616_OPCODE_VW_V_SHIFT, 1 },
.w = { X8616_OPCODE_VW_W_SHIFT, 1 },
@@ -592,10 +483,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
/* TEST r/m,reg: 1000010 w */ {
.opcode = {
.bits = x8616_opcode_test_rm_r << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_test_rm_r, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -604,10 +492,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* TEST r/m,imm: 1111011 w /0 */ {
.opcode = {
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_group3, X8616_OPCODE_W_PREFIX_SHIFT),
.mod_rm = {
.bits = x8616_g3_test << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
@@ -620,10 +505,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* TEST accumulator,imm: 1010100 w */ {
.opcode = {
.bits = x8616_opcode_test_acc_i << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_test_acc_i, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -634,10 +516,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
// String / prefixes-------------------------------------------------------
/* REP/REPNE prefix: 1111001 z */ {
.opcode = {
.bits = x8616_opcode_rep << X8616_OPCODE_Z_PREFIX_SHIFT,
.mask = X8616_OPCODE_Z_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_rep, X8616_OPCODE_Z_PREFIX_SHIFT),
.fields = {
.z = { X8616_OPCODE_Z_Z_SHIFT, 1 },
},
@@ -646,10 +525,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* MOVS: ... w */ {
.opcode = {
.bits = x8616_opcode_movs << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_movs, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -657,10 +533,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* CMPS: ... w */ {
.opcode = {
.bits = x8616_opcode_cmps << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_cmps, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -668,10 +541,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* SCAS: ... w */ {
.opcode = {
.bits = x8616_opcode_scas << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_scas, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -679,10 +549,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* LODS: ... w */ {
.opcode = {
.bits = x8616_opcode_lods << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_lods, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -690,10 +557,7 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* STOS: ... w */ {
.opcode = {
.bits = x8616_opcode_stos << X8616_OPCODE_W_PREFIX_SHIFT,
.mask = X8616_OPCODE_W_PREFIX_MASK,
},
.header = x8616_opc(x8616_opcode_stos, X8616_OPCODE_W_PREFIX_SHIFT),
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
@@ -701,19 +565,13 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* LOCK prefix */ {
.opcode = {
.bits = x8616_opcode_lock,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_lock),
.flags = x8616_encoding_prefix,
.op = x8616_op_lock,
},
/* Segment override: 001 sr 110 */ {
.opcode = {
.bits = X8616_OPCODE_SEG_FIXED,
.mask = X8616_OPCODE_SR_PATTERN_MASK,
},
.header = x8616_header_sr(x8616_opcode_sr_override, x8616_sr_low_push),
.fields = {
.sr = { X8616_OPCODE_SR_SHIFT, X8616_OPCODE_SR_WIDTH },
},
@@ -724,47 +582,41 @@ RO_ global X8616_Encoding x8616_encodings[] =
// Control transfer--------------------------------------------------------
/* CALL rel16 */ {
.opcode = {
.bits = x8616_opcode_call_rel16,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_call_rel16),
.operands = { x8616_operand_rel16 },
.op = x8616_op_call,
},
/* CALL r/m16: FF /2 */ {
.opcode = {
.bits = x8616_opcode_group_ff,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_header_w(x8616_opcode_incdec_rm, x8616_w_word),
.mod_rm = {
.bits = x8616_ff_call_near << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
},
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
.operands = { x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_call,
},
/* CALL far ptr16:16 */ {
.opcode = {
.bits = x8616_opcode_call_far,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_call_far),
.operands = { x8616_operand_far_ptr },
.flags = x8616_encoding_far,
.op = x8616_op_call,
},
/* CALL far r/m16: FF /3 */ {
.opcode = {
.bits = x8616_opcode_group_ff,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_header_w(x8616_opcode_incdec_rm, x8616_w_word),
.mod_rm = {
.bits = x8616_ff_call_far << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
},
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
.operands = { x8616_operand_rm },
.width = x8616_width_word,
.flags = x8616_encoding_far,
@@ -772,56 +624,47 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* JMP rel16 */ {
.opcode = {
.bits = x8616_opcode_jmp_rel16,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_jmp_rel16),
.operands = { x8616_operand_rel16 },
.op = x8616_op_jmp,
},
/* JMP rel8 */ {
.opcode = {
.bits = x8616_opcode_jmp_rel8,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_jmp_rel8),
.operands = { x8616_operand_rel8 },
.op = x8616_op_jmp,
},
/* JMP r/m16: FF /4 */ {
.opcode = {
.bits = x8616_opcode_group_ff,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_header_w(x8616_opcode_incdec_rm, x8616_w_word),
.mod_rm = {
.bits = x8616_ff_jmp_near << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
},
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
.operands = { x8616_operand_rm },
.width = x8616_width_word,
.op = x8616_op_jmp,
},
/* JMP far ptr16:16 */ {
.opcode = {
.bits = x8616_opcode_jmp_far,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_jmp_far),
.operands = { x8616_operand_far_ptr },
.flags = x8616_encoding_far,
.op = x8616_op_jmp,
},
/* JMP far r/m16: FF /5 */ {
.opcode = {
.bits = x8616_opcode_group_ff,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_header_w(x8616_opcode_incdec_rm, x8616_w_word),
.mod_rm = {
.bits = x8616_ff_jmp_far << X8616_MODRM_REG_SHIFT,
.mask = X8616_MODRM_REG_MASK,
},
.fields = {
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
},
.operands = { x8616_operand_rm },
.width = x8616_width_word,
.flags = x8616_encoding_far,
@@ -829,44 +672,29 @@ RO_ global X8616_Encoding x8616_encodings[] =
},
/* RET */ {
.opcode = {
.bits = x8616_opcode_ret,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_ret),
.op = x8616_op_ret,
},
/* RET imm16 */ {
.opcode = {
.bits = x8616_opcode_ret_i,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_ret_i),
.operands = { x8616_operand_imm16 },
.op = x8616_op_ret,
},
/* RETF */ {
.opcode = {
.bits = x8616_opcode_retf,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_retf),
.op = x8616_op_retf,
},
/* RETF imm16 */ {
.opcode = {
.bits = x8616_opcode_retf_i,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_retf_i),
.operands = { x8616_operand_imm16 },
.op = x8616_op_retf,
},
/* Jcc rel8: 0111 cccc */ {
.opcode = {
.bits = x8616_opcode_jcc << X8616_OPCODE_CC_PREFIX_SHIFT,
.mask = x8616_stem_mask(X8616_OPCODE_CC_PREFIX_SHIFT),
},
.header = x8616_opc(x8616_opcode_jcc, X8616_OPCODE_CC_PREFIX_SHIFT),
.fields = {
.cc = { X8616_OPCODE_CC_SHIFT, X8616_OPCODE_CC_WIDTH },
},
@@ -876,37 +704,25 @@ RO_ global X8616_Encoding x8616_encodings[] =
/* LOOPNZ rel8 */ {
.opcode = {
.bits = x8616_opcode_loopnz,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_loopnz),
.operands = { x8616_operand_rel8 },
.op = x8616_op_loopnz,
},
/* LOOPZ rel8 */ {
.opcode = {
.bits = x8616_opcode_loopz,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_loopz),
.operands = { x8616_operand_rel8 },
.op = x8616_op_loopz,
},
/* LOOP rel8 */ {
.opcode = {
.bits = x8616_opcode_loop,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_loop),
.operands = { x8616_operand_rel8 },
.op = x8616_op_loop,
},
/* JCXZ rel8 */ {
.opcode = {
.bits = x8616_opcode_jcxz,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_jcxz),
.operands = { x8616_operand_rel8 },
.op = x8616_op_jcxz,
},
@@ -914,107 +730,68 @@ RO_ global X8616_Encoding x8616_encodings[] =
// Interrupt / machine control--------------------------------------------
/* INT imm8 */ {
.opcode = {
.bits = x8616_opcode_int,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_int),
.operands = { x8616_operand_imm8 },
.op = x8616_op_int,
},
/* INT3 */ {
.opcode = {
.bits = x8616_opcode_int3,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_int3),
.op = x8616_op_int3,
},
/* INTO */ {
.opcode = {
.bits = x8616_opcode_into,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_into),
.op = x8616_op_into,
},
/* IRET */ {
.opcode = {
.bits = x8616_opcode_iret,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_iret),
.op = x8616_op_iret,
},
/* CLC */ {
.opcode = {
.bits = x8616_opcode_clc,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_clc),
.op = x8616_op_clc,
},
/* CMC */ {
.opcode = {
.bits = x8616_opcode_cmc,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_cmc),
.op = x8616_op_cmc,
},
/* STC */ {
.opcode = {
.bits = x8616_opcode_stc,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_stc),
.op = x8616_op_stc,
},
/* CLD */ {
.opcode = {
.bits = x8616_opcode_cld,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_cld),
.op = x8616_op_cld,
},
/* STD */ {
.opcode = {
.bits = x8616_opcode_std,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_std),
.op = x8616_op_std,
},
/* CLI */ {
.opcode = {
.bits = x8616_opcode_cli,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_cli),
.op = x8616_op_cli,
},
/* STI */ {
.opcode = {
.bits = x8616_opcode_sti,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_sti),
.op = x8616_op_sti,
},
/* HLT */ {
.opcode = {
.bits = x8616_opcode_hlt,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_hlt),
.op = x8616_op_hlt,
},
/* WAIT */ {
.opcode = {
.bits = x8616_opcode_wait,
.mask = X8616_OPCODE_MASK,
},
.header = x8616_opc_byte(x8616_opcode_wait),
.op = x8616_op_wait,
},