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https://github.com/Ed94/perfaware.git
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decoder
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#ifdef INTELLISENSE_DIRECTIVES
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# pragma once
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# include "duffle/dsl.h"
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# include "duffle/text.h"
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# include "duffle/win32.h"
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# include "encoder.h"
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# include "encoder_table.h"
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# include "decoder.h"
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# include "info.h"
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#endif
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enum {
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X8616_DECODE_GEN_MAX_AUX = 256 * 256,
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};
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typedef Struct_(X8616_DecodeGen) {
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X8616_DecodePlan plans[X8616_ENCODING_COUNT + 1];
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U2 dispatch[256];
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U1 aux[X8616_DECODE_GEN_MAX_AUX];
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U4 aux_count;
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U4 ambiguous_opcode_count;
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U4 verified_count;
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X8616_InfoList msgs;
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};
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typedef Struct_(X8616_DecodeGenInfo) {
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U4 plan_count;
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U4 aux_count;
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U4 ambiguous_opcode_count;
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U4 verified_count;
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X8616_InfoList msgs;
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};
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FI_ B1 x8616_decode_gen_operand_uses_modrm(X8616_Operand operand) {
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return operand == x8616_operand_rm || operand == x8616_operand_reg_modrm || operand == x8616_operand_segment_modrm;
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}
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FI_ B1 x8616_decode_gen_operand_uses_rm(X8616_Operand operand) { return operand == x8616_operand_rm; }
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internal X8616_DecodePayload
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x8616_decode_gen_payload_from_operand(X8616_Operand operand) {
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switch (operand) {
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case x8616_operand_imm: return x8616_payload_imm;
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case x8616_operand_imm8: return x8616_payload_imm8;
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case x8616_operand_imm16: return x8616_payload_imm16;
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case x8616_operand_mem_direct: return x8616_payload_mem_direct;
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case x8616_operand_rel8: return x8616_payload_rel8;
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case x8616_operand_rel16: return x8616_payload_rel16;
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case x8616_operand_far_ptr: return x8616_payload_far_ptr;
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default: return x8616_payload_none;
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}
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}
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internal X8616_DecodePrefixKind
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x8616_decode_gen_prefix_kind(X8616_Encoding const* encoding) {
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if ((encoding->flags & x8616_encoding_prefix) == 0) return x8616_prefix_none;
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switch (encoding->op) {
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case x8616_op_lock: return x8616_prefix_lock;
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case x8616_op_rep: return x8616_prefix_repeat;
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case x8616_op_segment: return x8616_prefix_segment;
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default: return x8616_prefix_none;
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}
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}
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internal X8616_DecodePlan
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x8616_decode_gen_plan(X8616_Encoding const* encoding, U4 encoding_idx, X8616_InfoList* msgs, FArena_R info_scratch)
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{
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X8616_DecodePlan plan = {0};
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plan.op = encoding->op;
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plan.encoding_flags = encoding->flags;
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plan.width = encoding->width;
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plan.operands[0] = encoding->operands[0];
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plan.operands[1] = encoding->operands[1];
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plan.operand_count = (encoding->operands[0] != x8616_operand_none) + (encoding->operands[1] != x8616_operand_none);
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plan.prefix_kind = x8616_decode_gen_prefix_kind(encoding);
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plan.mod_rm = encoding->mod_rm;
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plan.post_opcode = encoding->post_opcode;
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if (encoding->mod_rm.mask || x8616_decode_gen_operand_uses_modrm(encoding->operands[0]) || x8616_decode_gen_operand_uses_modrm(encoding->operands[1]))
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plan.flags |= x8616_plan_has_modrm;
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if (encoding->post_opcode.mask)
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plan.flags |= x8616_plan_has_post_opcode;
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if (encoding->fields.d.width) { plan.flags |= x8616_plan_has_d; plan.d_shift = encoding->fields.d.shift; }
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if (encoding->fields.w.width) { plan.flags |= x8616_plan_has_w; plan.w_shift = encoding->fields.w.shift; }
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if (encoding->fields.s.width) { plan.flags |= x8616_plan_has_s; plan.s_shift = encoding->fields.s.shift; }
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if (encoding->fields.v.width) { plan.flags |= x8616_plan_has_v; plan.v_shift = encoding->fields.v.shift; }
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if (encoding->fields.z.width) { plan.flags |= x8616_plan_has_z; plan.z_shift = encoding->fields.z.shift; }
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if (encoding->fields.reg.width) { plan.flags |= x8616_plan_has_reg; plan.reg_shift = encoding->fields.reg.shift; }
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if (encoding->fields.sr.width) { plan.flags |= x8616_plan_has_sr; plan.sr_shift = encoding->fields.sr.shift; }
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if (x8616_decode_gen_operand_uses_rm(encoding->operands[0]) || x8616_decode_gen_operand_uses_rm(encoding->operands[1]))
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plan.flags |= x8616_plan_uses_rm;
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if (encoding->flags & x8616_encoding_prefix)
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plan.flags |= x8616_plan_is_prefix;
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X8616_DecodePayload payload_0 = x8616_decode_gen_payload_from_operand(encoding->operands[0]);
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X8616_DecodePayload payload_1 = x8616_decode_gen_payload_from_operand(encoding->operands[1]);
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if (payload_0 && payload_1 && payload_0 != payload_1)
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x8616_info_push(info_scratch, msgs, x8616_info_error, x8616_info_gen_multiple_payloads, encoding_idx, 0, payload_0, payload_1);
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plan.payload = payload_0 ? payload_0 : payload_1;
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U4 payload_max = 0;
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switch (plan.payload) {
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case x8616_payload_imm: payload_max = 2; break;
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case x8616_payload_imm8: payload_max = 1; break;
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case x8616_payload_imm16: payload_max = 2; break;
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case x8616_payload_mem_direct: payload_max = 2; break;
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case x8616_payload_rel8: payload_max = 1; break;
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case x8616_payload_rel16: payload_max = 2; break;
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case x8616_payload_far_ptr: payload_max = 4; break;
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default: break;
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}
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U4 body_max = 1
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+ ((plan.flags & x8616_plan_has_post_opcode) != 0)
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+ ((plan.flags & x8616_plan_has_modrm) != 0)
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+ ((plan.flags & x8616_plan_uses_rm) ? 2 : 0)
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+ payload_max;
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if (body_max > X8616_DECODE_BODY_CAP) x8616_info_push(info_scratch, msgs, x8616_info_error
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, x8616_info_gen_body_cap_exceeded
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, encoding_idx
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, 0
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, X8616_DECODE_BODY_CAP
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, body_max
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);
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return plan;
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}
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FI_ B1 x8616_decode_gen_encoding_matches_opcode(X8616_Encoding const* encoding, U1 opcode) {
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return (opcode & encoding->opcode.mask) == encoding->opcode.bits;
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}
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FI_ B1 x8616_decode_gen_plan_matches_second(X8616_DecodePlan const* plan, U1 byte) {
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if (plan->mod_rm.mask && ((byte & plan->mod_rm.mask) != plan->mod_rm.bits)) return false;
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if (plan->post_opcode.mask && ((byte & plan->post_opcode.mask) != plan->post_opcode.bits)) return false;
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return true;
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}
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internal void x8616_decode_gen_pass_plans(X8616_DecodeGen* gen, FArena_R info_scratch) {
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for (U4 idx = 0; idx < X8616_ENCODING_COUNT; ++ idx)
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gen->plans[idx + 1] = x8616_decode_gen_plan(x8616_encodings + idx, idx, & gen->msgs, info_scratch);
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}
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internal void
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x8616_decode_gen_pass_dispatch(X8616_DecodeGen* gen, FArena_R info_scratch)
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{
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for (U4 opcode = 0; opcode < 256; ++ opcode)
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{
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U1 candidates[X8616_ENCODING_COUNT];
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U4 candidate_count = 0;
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for (U4 encoding_idx = 0; encoding_idx < X8616_ENCODING_COUNT; ++ encoding_idx)
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if (x8616_decode_gen_encoding_matches_opcode(x8616_encodings + encoding_idx, C_(U1, opcode)))
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candidates[candidate_count ++] = C_(U1, encoding_idx + 1);
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if (candidate_count == 0) continue;
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if (candidate_count == 1) { gen->dispatch[opcode] = candidates[0]; continue; }
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if (gen->aux_count + 256 > X8616_DECODE_GEN_MAX_AUX) {
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x8616_info_push(info_scratch, & gen->msgs, x8616_info_error
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, x8616_info_gen_aux_cap_exceeded
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, opcode
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, 0
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, X8616_DECODE_GEN_MAX_AUX
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, gen->aux_count + 256
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);
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return;
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}
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U4 base = gen->aux_count;
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gen->dispatch[opcode] = C_(U2, X8616_DECODE_AUX_BIT | base);
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gen->aux_count += 256;
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gen->ambiguous_opcode_count += 1;
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for (U4 second = 0; second < 256; ++ second)
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{
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U1 selected = 0;
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for (U4 candidate_idx = 0; candidate_idx < candidate_count; ++ candidate_idx)
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{
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U1 plan_idx = candidates[candidate_idx];
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if (! x8616_decode_gen_plan_matches_second(gen->plans + plan_idx, C_(U1, second)))
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continue;
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if (selected) x8616_info_push(info_scratch, & gen->msgs, x8616_info_error
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, x8616_info_gen_ambiguous_decode
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, (opcode << 8) | second
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, 0
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, selected
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, plan_idx
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);
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selected = plan_idx;
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}
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gen->aux[base + second] = selected;
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}
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}
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}
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internal void
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x8616_decode_gen_pass_validate(X8616_DecodeGen* gen, FArena_R info_scratch)
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{
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for (U4 opcode = 0; opcode < 256; ++ opcode)
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for (U4 second = 0; second < 256; ++ second)
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{
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U1 expected = 0;
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for (U4 encoding_idx = 0; encoding_idx < X8616_ENCODING_COUNT; ++ encoding_idx)
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{
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X8616_Encoding const* encoding = x8616_encodings + encoding_idx;
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if (! x8616_decode_gen_encoding_matches_opcode(encoding, C_(U1, opcode))) continue;
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X8616_DecodePlan const* plan = gen->plans + encoding_idx + 1;
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if (! x8616_decode_gen_plan_matches_second(plan, C_(U1, second))) continue;
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if (expected) x8616_info_push(info_scratch, & gen->msgs, x8616_info_error
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, x8616_info_gen_ambiguous_decode
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, (opcode << 8) | second, 0
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, expected, encoding_idx + 1
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);
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expected = C_(U1, encoding_idx + 1);
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}
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U2 dispatch = gen->dispatch[opcode];
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U1 actual = 0;
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if (dispatch & X8616_DECODE_AUX_BIT) {
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U2 base = dispatch & X8616_DECODE_AUX_MASK;
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actual = gen->aux[base + second];
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}
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else if (dispatch) {
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U1 candidate = C_(U1, dispatch);
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if (x8616_decode_gen_plan_matches_second(gen->plans + candidate, C_(U1, second)))
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actual = candidate;
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}
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if (actual != expected) x8616_info_push(info_scratch, & gen->msgs, x8616_info_error
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, x8616_info_gen_dispatch_mismatch
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, (opcode << 8) | second, 0
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, expected, actual
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);
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++ gen->verified_count;
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}
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}
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X8616_DecodeGenInfo
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x8616_decode_table_generate(X8616_DecodeGen* gen, FArena_R info_scratch) {
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gen[0] = (X8616_DecodeGen){0};
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x8616_decode_gen_pass_plans (gen, info_scratch);
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x8616_decode_gen_pass_dispatch(gen, info_scratch);
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x8616_decode_gen_pass_validate(gen, info_scratch);
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X8616_DecodeGenInfo result = {
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.plan_count = X8616_ENCODING_COUNT + 1,
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.aux_count = gen->aux_count,
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.ambiguous_opcode_count = gen->ambiguous_opcode_count,
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.verified_count = gen->verified_count,
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.msgs = gen->msgs,
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};
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return result;
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}
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