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      "post_id": "2077224595858280506",
      "author": "NOTimothyLottes",
      "handle": "NOTimothyLottes",
      "text": "One advantage of SAR (aka signed '>>') is that the shift-by operand HW uses only the 5|6 LSBs automatically. So if you have a mixed used control word, you don't have to mask out the MSBs. Can save an instruction.",
      "timestamp": "2026-07-15 02:51:51",
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      "post_id": "2077225347049767246",
      "author": "NOTimothyLottes",
      "handle": "NOTimothyLottes",
      "text": "Working through an idea of a single uber-instruction interpreted language for code generation. Meaning something that never misses the instruction cache and executes fully out of the micro-op cache. Fully data driven with a direct map 64k entry symbol table.",
      "timestamp": "2026-07-15 02:54:50",
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    {
      "post_id": "2077227411112870280",
      "author": "NOTimothyLottes",
      "handle": "NOTimothyLottes",
      "text": "Borrows some ideas from SIMD GPU programming. Like instead of branching/predicating to avoid stores, just store to a discarded area (like a negative offset on the GPU, or a designated trash address on the CPU).",
      "timestamp": "2026-07-15 03:03:02",
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      "post_id": "2077234537302556898",
      "author": "NOTimothyLottes",
      "handle": "NOTimothyLottes",
      "text": "Don't want exit condition logic in the infinite loop, so exit will have to be having the program store an exit value into a set address, and an external watchdog polling for exit at some sleep frequency.",
      "timestamp": "2026-07-15 03:31:21",
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      "post_id": "2077241596869751029",
      "author": "NOTimothyLottes",
      "handle": "NOTimothyLottes",
      "text": "SAR on a control word can in theory grab 3 values.\nSF (sign flag) is set to MSB bit\nCF (carry flag) is set to what shifts into bit -1\nand output\n\nThe SF and CF can be used for CMOVcc\nOutput can be used for another shift (after CMOVccs)",
      "timestamp": "2026-07-15 03:59:24",
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