From ef5e8246940661e6db287510e9866cb0f920cfeb Mon Sep 17 00:00:00 2001 From: Ed_ Date: Mon, 27 Jul 2026 13:01:23 -0400 Subject: [PATCH] docs(twitter): add 1735622924571201674 corpus (NOTimothyLottes Holiday GPU thoughts 2023) 25-post thread, 0 media, 2023-12-15. HIGHEST engagement 2023 thread: 112 likes, 25 reposts, 31576 views. 'Holiday GPU thoughts as a recovering pc/mobile/etc cross platform dev-holic' - the 16-bit permutation philosophy + post-black-box philosophy in one thread. [0] STP prototypes: 32-bit multi-dispatch vs packed-16 single- dispatch-ubershader, 40% faster, 'Industry has huge untapped opt potential.' [1-7] 16-bit fundamentals: AMD Vega+ for PC, draw compatibility line at 16-bit, dev on AMD VK RDNA2 + avoid DXC deoptimizer, Gather4 SoA, range management, denormals, Touch It Once is top optimization, no pass-graph fragmentation. [8-12] TAA scaling: 720p/1080p rendering for 4k, large L3 holds full render targets, RDNA2's 128 MiB L3 was spot on, RDNA3 drop was wrong, console no-L3 was wrong. [13-17] Triangles obsolete: 8x area scaling doesn't know connectivity, scaling TAA = mostly tri culling, fix geometrical aliasing to break black boxes, stratified sampling 2x geo density, frame viewport jitter EOL, TAA disocclusion deeply integrated into shading. [18-23] ML/GI/RT critique: per-pixel ML people wrong, multi-pass vs fewer-passes, GI needs surface shade cache -> object-space shading -> NUMA, HW RT people wrong (non-ray-traversal ordered access, occlusion = neighbor-coherent, GI = high-freq occlusion of low-freq probe domain, HW RT skin-all re-tree won't scale, stratified visibility = bounded costs). [24] Vote with engineering: general-purpose CS, say no to black boxes. [25] Scaling TAA wants sparse striped data per frame, low-freq pixel control cage displacing high-freq reprojected feedback. --- docs/twitter/1735622924571201674/thread.md | 117 +++++ .../1735622924571201674/thread_data.json | 406 ++++++++++++++++++ 2 files changed, 523 insertions(+) create mode 100644 docs/twitter/1735622924571201674/thread.md create mode 100644 docs/twitter/1735622924571201674/thread_data.json diff --git a/docs/twitter/1735622924571201674/thread.md b/docs/twitter/1735622924571201674/thread.md new file mode 100644 index 00000000..2384d231 --- /dev/null +++ b/docs/twitter/1735622924571201674/thread.md @@ -0,0 +1,117 @@ +--- +title: " " +author: "NOTimothyLottes" +handle: "@NOTimothyLottes" +post_url: "https://x.com/NOTimothyLottes/status/1735622924571201674" +post_id: "1735622924571201674" +timestamp: "2023-12-15 11:28:46" +post_count: 25 +reply_count: 1 +repost_count: 25 +like_count: 112 +view_count: 31576 +--- + +# @NOTimothyLottes — + +## Post 1 (2023-12-15 11:28:46) + + +Holiday GPU thoughts as a recovering pc/mobile/etc cross platform dev-holic ... + +## Post 2 (2023-12-15 11:29:58) — reply to Post 1 + +[0] Early STP prototypes: had standard-PC-practice multi-dispatch 32-bit version, and hyper-optimized packed-16-bit semi-persistent single-dispatch-ubershader that got L2 reuse. Optimized one was 40% faster in profiling (VK RNDA2 GPU)! Industry has huge untapped opt potential + +## Post 3 (2023-12-15 11:31:27) — reply to Post 2 + +[1] Even for PC, 16-bit is required for optimization because: almost double the amount of register state a shader can leverage. Holds true even when platform lacks double rate 16-bit. Top optimization is pass merging, PC went bandwidth starved. Mobile is actually ALU starved ... + +## Post 4 (2023-12-15 11:31:52) — reply to Post 3 + +[2] Double rate 16-bit done right, is typically good for the smaller of {30% perf, return to non-ALU bound}, can make a GPU feel at least one HW generation faster. + +## Post 5 (2023-12-15 11:32:22) — reply to Post 4 + +[3] For PC, I'd personally draw my compatibility line where platforms support 16-bit, and only ship explicit packed 16-bit shaders instead of a separate 32-bit/16-bit shader permutation. AMD it's Vega up, for NV note Maxwell/Pascal's HFMA2: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html#maxwell-and-pascal-instruction-set + +## Post 6 (2023-12-15 11:33:00) — reply to Post 5 + +[4] Suggest doing dev work on a platform with great packed 16-bit support: AMD PC Vulkan on RDNA2, and don't filter through the DXC deoptimizer, so it is actually possible to see the value. Then hammer on vendors who still have spotty compiler related issues. + +## Post 7 (2023-12-15 11:33:38) — reply to Post 6 + +[5] Gather4 is the hot optimization for packed 16-bit because data is returned in SoA form. Always explicitly pack 16-bit and alias to/from UINT32 when passing constants to shader (best to alias eight 16-bit values as uint4). Etc. + +## Post 8 (2023-12-15 11:34:44) — reply to Post 7 + +[6] Trick for good 16-bit is range management. Sometimes pre-scaling is needed to avoid overflow, +and make sure to bring max values out of denormal before using rcp. + +## Post 9 (2023-12-15 11:35:23) — reply to Post 8 + +[7] Power is a function of data movement. "Touch it Once" is the top optimization, all the "Split it into a Graph, Pipeline Stage it" people are walking themselves towards high-power. + +## Post 10 (2023-12-15 11:36:13) — reply to Post 9 + +[8] Majority of GPU workloads are whole-pass serially dependent, but in practice temporally independent with exception of small localized serial dependency. If you "stick it into a frame graph" you cut off your ability to optimize. + +## Post 11 (2023-12-15 11:36:48) — reply to Post 10 + +[9] Resolution growth is slowing. Mobile's high DPI is beyond good enough. 8k won't be successfull because of the extra 4x scaling TAA tax, or it won't matter because people will just integer scale on scanout. + +## Post 12 (2023-12-15 11:38:15) — reply to Post 11 + +[10] Scaling TAA will converge to consistent higher quality over time, thus PC is likely to locally converge to 720p|1080p rendering for 4k (for high|med FPS). This implies that the industry should hit a point where large L3 can hold full render targets ... + +## Post 13 (2023-12-15 11:39:17) — reply to Post 12 + +[11] TAA scaling, full render targets in L3: Maybe RDNA2 128 MiB L3 was spot on actually, and RNDA3's L3 drop in capacity, and the no L3 consoles had this wrong Tracing and big nets probably need that L3 too. + +## Post 14 (2023-12-15 11:40:16) — reply to Post 13 + +[12] Lots of value getting a good 8x area scale for 4K 120 Hz. Yet devs won't see value until they make the non-pixel costs scale well, and move post before scaling. + +## Post 15 (2023-12-15 11:41:52) — reply to Post 14 + +[13] Triangles are not needed any more. Hint 8x area scaling doesn't know any connectivity. Connectivity is inferred by likeness to accumulated feedback. Shaded samples from non-triangles -> scaling TAA still works. Hint 2: scaling TAA raster is mostly just tri culling. + +## Post 16 (2023-12-15 11:42:40) — reply to Post 15 + +[14] TAA gets quality limited at high scaling because it can only infer correct behavior from geometry similar to what is rendered. Geometric aliasing drops too much thin geo. Fix for that is to change the standard practice, which will obsolete all black boxes. + +## Post 17 (2023-12-15 11:43:31) — reply to Post 16 + +[15] Stratified sampling is good for at least 2x the geo density compared to regular grid ... frame viewport jitter is end-of-life for quality. + +## Post 18 (2023-12-15 11:44:08) — reply to Post 17 + +[16] TAA's ability to correctly infer reprojection validity on skinned objects is crippled by lack of correct forward projection. Fixing that will break the black boxes. + +## Post 19 (2023-12-15 11:45:05) — reply to Post 18 + +[17] Shading density will end up variable, TAA's disocclusion and convergence logic needs to be out of the black box, and deeply integrated into shading systems too (because it points where to shade more). This evolution will break all the black boxes. + +## Post 20 (2023-12-15 11:46:08) — reply to Post 19 + +[18] Per-pixel ML people have it wrong, your net is multi-pass, all the top optimizations require less passes. Don't matter if you optimize the matrix math, power is burned in the bandwidth, and you cannot reduce your bandwidth enough to compete with the better options. + +## Post 21 (2023-12-15 11:48:52) — reply to Post 20 + +[19] GI needs a surface shade cache, might as well object space shade at that point, which enables NUMA, which enables more HW scaling. + +## Post 22 (2023-12-15 11:50:04) — reply to Post 21 + +[20] HW RT people had it very wrong, top optimization is non-ray-traversal ordered access. Follows: occlusion testing is neighbor-coherent, no trace, just test shared occluders. GI reduces to high frequency occlusion of some lower frequency probe domain. + +## Post 23 (2023-12-15 11:51:16) — reply to Post 22 + +[21] HW RT's skin-all re-tree before trace won't scale ever. Only stratified visibility gets log scaling on animated geo. HW RT has no system for bounding costs, while stratified visibility does. Think out of the black box, GPU got programmability decade back now. + +## Post 24 (2023-12-15 12:04:08) — reply to Post 23 + +[22] Love HW people, but they opt for a $ train even as it is derailing: they need to build HW, make it faster, it's what they do. But leave a trail of back-compat debris TS/ROV/GS/etc after each gfx fad. Vote with your engineering, general purpose CS, just say no to black boxes. + +## Post 25 (2023-12-15 13:17:31) — reply to Post 24 + +[23] Scaling TAAs want sparse data each frame, more like a low-frequency pixel control cage displacing a high-frequency reprojected feedback. No pixel centers any more, no need to interpolate before shading. Rather want striped data, so the cachelines group spaced-out samples ... diff --git a/docs/twitter/1735622924571201674/thread_data.json b/docs/twitter/1735622924571201674/thread_data.json new file mode 100644 index 00000000..6cb85699 --- /dev/null +++ b/docs/twitter/1735622924571201674/thread_data.json @@ -0,0 +1,406 @@ +{ + "root_post_id": "1735622924571201674", + "posts": [ + { + "post_id": "1735622924571201674", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": " \nHoliday GPU thoughts as a recovering pc/mobile/etc cross platform dev-holic ...", + "timestamp": "2023-12-15 11:28:46", + "media_urls": [], + "reply_to_id": null, + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 25, + "like_count": 112, + "view_count": 31576 + } + }, + { + "post_id": "1735623225860583609", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[0] Early STP prototypes: had standard-PC-practice multi-dispatch 32-bit version, and hyper-optimized packed-16-bit semi-persistent single-dispatch-ubershader that got L2 reuse. Optimized one was 40% faster in profiling (VK RNDA2 GPU)! Industry has huge untapped opt potential", + "timestamp": "2023-12-15 11:29:58", + "media_urls": [], + "reply_to_id": "1735622924571201674", + "quote_of_id": null, + "metrics": { + "reply_count": 2, + "repost_count": 0, + "like_count": 7, + "view_count": 2204 + } + }, + { + "post_id": "1735623600344813976", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[1] Even for PC, 16-bit is required for optimization because: almost double the amount of register state a shader can leverage. Holds true even when platform lacks double rate 16-bit. Top optimization is pass merging, PC went bandwidth starved. Mobile is actually ALU starved ...", + "timestamp": "2023-12-15 11:31:27", + "media_urls": [], + "reply_to_id": "1735623225860583609", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 5, + "view_count": 2141 + } + }, + { + "post_id": "1735623707001753932", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[2] Double rate 16-bit done right, is typically good for the smaller of {30% perf, return to non-ALU bound}, can make a GPU feel at least one HW generation faster.", + "timestamp": "2023-12-15 11:31:52", + "media_urls": [], + "reply_to_id": "1735623600344813976", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 3, + "view_count": 1843 + } + }, + { + "post_id": "1735623832549916904", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[3] For PC, I'd personally draw my compatibility line where platforms support 16-bit, and only ship explicit packed 16-bit shaders instead of a separate 32-bit/16-bit shader permutation. AMD it's Vega up, for NV note Maxwell/Pascal's HFMA2: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html#maxwell-and-pascal-instruction-set", + "timestamp": "2023-12-15 11:32:22", + "media_urls": [], + "reply_to_id": "1735623707001753932", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 5, + "view_count": 1696 + } + }, + { + "post_id": "1735623992961081680", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[4] Suggest doing dev work on a platform with great packed 16-bit support: AMD PC Vulkan on RDNA2, and don't filter through the DXC deoptimizer, so it is actually possible to see the value. Then hammer on vendors who still have spotty compiler related issues.", + "timestamp": "2023-12-15 11:33:00", + "media_urls": [], + "reply_to_id": "1735623832549916904", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 3, + "view_count": 1540 + } + }, + { + "post_id": "1735624151283478999", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[5] Gather4 is the hot optimization for packed 16-bit because data is returned in SoA form. Always explicitly pack 16-bit and alias to/from UINT32 when passing constants to shader (best to alias eight 16-bit values as uint4). Etc.", + "timestamp": "2023-12-15 11:33:38", + "media_urls": [], + "reply_to_id": "1735623992961081680", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 7, + "view_count": 1407 + } + }, + { + "post_id": "1735624428581429681", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[6] Trick for good 16-bit is range management. Sometimes pre-scaling is needed to avoid overflow,\nand make sure to bring max values out of denormal before using rcp.", + "timestamp": "2023-12-15 11:34:44", + "media_urls": [], + "reply_to_id": "1735624151283478999", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 3, + "view_count": 1298 + } + }, + { + "post_id": "1735624590997573967", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[7] Power is a function of data movement. \"Touch it Once\" is the top optimization, all the \"Split it into a Graph, Pipeline Stage it\" people are walking themselves towards high-power.", + "timestamp": "2023-12-15 11:35:23", + "media_urls": [], + "reply_to_id": "1735624428581429681", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 1, + "like_count": 9, + "view_count": 1790 + } + }, + { + "post_id": "1735624799378923763", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[8] Majority of GPU workloads are whole-pass serially dependent, but in practice temporally independent with exception of small localized serial dependency. If you \"stick it into a frame graph\" you cut off your ability to optimize.", + "timestamp": "2023-12-15 11:36:13", + "media_urls": [], + "reply_to_id": "1735624590997573967", + "quote_of_id": null, + "metrics": { + "reply_count": 2, + "repost_count": 0, + "like_count": 2, + "view_count": 1204 + } + }, + { + "post_id": "1735624946414501895", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[9] Resolution growth is slowing. Mobile's high DPI is beyond good enough. 8k won't be successfull because of the extra 4x scaling TAA tax, or it won't matter because people will just integer scale on scanout.", + "timestamp": "2023-12-15 11:36:48", + "media_urls": [], + "reply_to_id": "1735624799378923763", + "quote_of_id": null, + "metrics": { + "reply_count": 2, + "repost_count": 0, + "like_count": 2, + "view_count": 1154 + } + }, + { + "post_id": "1735625312350642210", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[10] Scaling TAA will converge to consistent higher quality over time, thus PC is likely to locally converge to 720p|1080p rendering for 4k (for high|med FPS). This implies that the industry should hit a point where large L3 can hold full render targets ...", + "timestamp": "2023-12-15 11:38:15", + "media_urls": [], + "reply_to_id": "1735624946414501895", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 3, + "view_count": 1117 + } + }, + { + "post_id": "1735625572040994994", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[11] TAA scaling, full render targets in L3: Maybe RDNA2 128 MiB L3 was spot on actually, and RNDA3's L3 drop in capacity, and the no L3 consoles had this wrong Tracing and big nets probably need that L3 too.", + "timestamp": "2023-12-15 11:39:17", + "media_urls": [], + "reply_to_id": "1735625312350642210", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 1, + "view_count": 1040 + } + }, + { + "post_id": "1735625818288558341", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[12] Lots of value getting a good 8x area scale for 4K 120 Hz. Yet devs won't see value until they make the non-pixel costs scale well, and move post before scaling.", + "timestamp": "2023-12-15 11:40:16", + "media_urls": [], + "reply_to_id": "1735625572040994994", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 3, + "view_count": 992 + } + }, + { + "post_id": "1735626224188243980", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[13] Triangles are not needed any more. Hint 8x area scaling doesn't know any connectivity. Connectivity is inferred by likeness to accumulated feedback. Shaded samples from non-triangles -> scaling TAA still works. Hint 2: scaling TAA raster is mostly just tri culling.", + "timestamp": "2023-12-15 11:41:52", + "media_urls": [], + "reply_to_id": "1735625818288558341", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 2, + "view_count": 983 + } + }, + { + "post_id": "1735626424956895544", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[14] TAA gets quality limited at high scaling because it can only infer correct behavior from geometry similar to what is rendered. Geometric aliasing drops too much thin geo. Fix for that is to change the standard practice, which will obsolete all black boxes.", + "timestamp": "2023-12-15 11:42:40", + "media_urls": [], + "reply_to_id": "1735626224188243980", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 1, + "view_count": 979 + } + }, + { + "post_id": "1735626636509208780", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[15] Stratified sampling is good for at least 2x the geo density compared to regular grid ... frame viewport jitter is end-of-life for quality.", + "timestamp": "2023-12-15 11:43:31", + "media_urls": [], + "reply_to_id": "1735626424956895544", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 2, + "view_count": 961 + } + }, + { + "post_id": "1735626794491949057", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[16] TAA's ability to correctly infer reprojection validity on skinned objects is crippled by lack of correct forward projection. Fixing that will break the black boxes.", + "timestamp": "2023-12-15 11:44:08", + "media_urls": [], + "reply_to_id": "1735626636509208780", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 1, + "view_count": 956 + } + }, + { + "post_id": "1735627033844085045", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[17] Shading density will end up variable, TAA's disocclusion and convergence logic needs to be out of the black box, and deeply integrated into shading systems too (because it points where to shade more). This evolution will break all the black boxes.", + "timestamp": "2023-12-15 11:45:05", + "media_urls": [], + "reply_to_id": "1735626794491949057", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 3, + "view_count": 1020 + } + }, + { + "post_id": "1735627294377456031", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[18] Per-pixel ML people have it wrong, your net is multi-pass, all the top optimizations require less passes. Don't matter if you optimize the matrix math, power is burned in the bandwidth, and you cannot reduce your bandwidth enough to compete with the better options.", + "timestamp": "2023-12-15 11:46:08", + "media_urls": [], + "reply_to_id": "1735627033844085045", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 4, + "view_count": 1016 + } + }, + { + "post_id": "1735627982763385283", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[19] GI needs a surface shade cache, might as well object space shade at that point, which enables NUMA, which enables more HW scaling.", + "timestamp": "2023-12-15 11:48:52", + "media_urls": [], + "reply_to_id": "1735627294377456031", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 6, + "view_count": 1044 + } + }, + { + "post_id": "1735628284979777660", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[20] HW RT people had it very wrong, top optimization is non-ray-traversal ordered access. Follows: occlusion testing is neighbor-coherent, no trace, just test shared occluders. GI reduces to high frequency occlusion of some lower frequency probe domain.", + "timestamp": "2023-12-15 11:50:04", + "media_urls": [], + "reply_to_id": "1735627982763385283", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 4, + "view_count": 1064 + } + }, + { + "post_id": "1735628590094385329", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[21] HW RT's skin-all re-tree before trace won't scale ever. Only stratified visibility gets log scaling on animated geo. HW RT has no system for bounding costs, while stratified visibility does. Think out of the black box, GPU got programmability decade back now.", + "timestamp": "2023-12-15 11:51:16", + "media_urls": [], + "reply_to_id": "1735628284979777660", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 3, + "view_count": 1206 + } + }, + { + "post_id": "1735631826427732305", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[22] Love HW people, but they opt for a $ train even as it is derailing: they need to build HW, make it faster, it's what they do. But leave a trail of back-compat debris TS/ROV/GS/etc after each gfx fad. Vote with your engineering, general purpose CS, just say no to black boxes.", + "timestamp": "2023-12-15 12:04:08", + "media_urls": [], + "reply_to_id": "1735628590094385329", + "quote_of_id": null, + "metrics": { + "reply_count": 2, + "repost_count": 0, + "like_count": 11, + "view_count": 1770 + } + }, + { + "post_id": "1735650294552203454", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "[23] Scaling TAAs want sparse data each frame, more like a low-frequency pixel control cage displacing a high-frequency reprojected feedback. No pixel centers any more, no need to interpolate before shading. Rather want striped data, so the cachelines group spaced-out samples ...", + "timestamp": "2023-12-15 13:17:31", + "media_urls": [], + "reply_to_id": "1735631826427732305", + "quote_of_id": null, + "metrics": { + "reply_count": 0, + "repost_count": 0, + "like_count": 2, + "view_count": 1426 + } + } + ], + "source_url": "https://x.com/NOTimothyLottes/status/1735622924571201674" +} \ No newline at end of file