From 9e2ff29841aa7bc83a5b656c6ac3ebd057d6cc43 Mon Sep 17 00:00:00 2001 From: Ed_ Date: Mon, 27 Jul 2026 10:43:43 -0400 Subject: [PATCH] docs(twitter): add 2077241596869751029 corpus (NOTimothyLottes uber-instruction interp language) 5-post thread, 0 media, July 2026. SAR (signed shift-right) trick: HW uses only 5|6 LSBs of shift-by so mixed-use control words don't need MSB masking - saves an instruction. Working through a single uber-instruction interpreted language for code generation: never misses the instruction cache, executes fully out of micro-op cache, fully data driven, direct map 64K entry symbol table. Borrows from SIMD GPU programming: instead of branching/predicating to avoid stores, just store to a discarded area (negative offset on GPU, designated trash address on CPU). No exit condition logic in infinite loop - exit via storing to set address, external watchdog polls at some sleep frequency. SAR trick can grab 3 values: SF (MSB), CF (shift-out bit -1), and output - SF+CF for CMOVcc, output for next shift. Sibling to the 2079746130309415185 micro macro-forth and 2078349730204078527 8-byte aligned Forth word threads - the uber-instruction version of the runtime-language work. --- docs/twitter/2077241596869751029/thread.md | 41 +++++++++ .../2077241596869751029/thread_data.json | 86 +++++++++++++++++++ 2 files changed, 127 insertions(+) create mode 100644 docs/twitter/2077241596869751029/thread.md create mode 100644 docs/twitter/2077241596869751029/thread_data.json diff --git a/docs/twitter/2077241596869751029/thread.md b/docs/twitter/2077241596869751029/thread.md new file mode 100644 index 00000000..998bd035 --- /dev/null +++ b/docs/twitter/2077241596869751029/thread.md @@ -0,0 +1,41 @@ +--- +title: "SAR on a control word can in theory grab 3 values." +author: "NOTimothyLottes" +handle: "@NOTimothyLottes" +post_url: "https://x.com/NOTimothyLottes/status/2077241596869751029" +post_id: "2077241596869751029" +timestamp: "2026-07-15 03:59:24" +post_count: 5 +reply_count: 0 +repost_count: 0 +like_count: 2 +view_count: 428 +--- + +# @NOTimothyLottes — SAR on a control word can in theory grab 3 values. + +## Post 1 (2026-07-15 02:51:51) + +One advantage of SAR (aka signed '>>') is that the shift-by operand HW uses only the 5|6 LSBs automatically. So if you have a mixed used control word, you don't have to mask out the MSBs. Can save an instruction. + +## Post 2 (2026-07-15 02:54:50) — reply to Post 1 + +Working through an idea of a single uber-instruction interpreted language for code generation. Meaning something that never misses the instruction cache and executes fully out of the micro-op cache. Fully data driven with a direct map 64k entry symbol table. + +## Post 3 (2026-07-15 03:03:02) — reply to Post 2 + +Borrows some ideas from SIMD GPU programming. Like instead of branching/predicating to avoid stores, just store to a discarded area (like a negative offset on the GPU, or a designated trash address on the CPU). + +## Post 4 (2026-07-15 03:31:21) — reply to Post 3 + +Don't want exit condition logic in the infinite loop, so exit will have to be having the program store an exit value into a set address, and an external watchdog polling for exit at some sleep frequency. + +## Post 5 (2026-07-15 03:59:24) — reply to Post 4 + +SAR on a control word can in theory grab 3 values. +SF (sign flag) is set to MSB bit +CF (carry flag) is set to what shifts into bit -1 +and output + +The SF and CF can be used for CMOVcc +Output can be used for another shift (after CMOVccs) diff --git a/docs/twitter/2077241596869751029/thread_data.json b/docs/twitter/2077241596869751029/thread_data.json new file mode 100644 index 00000000..589650c8 --- /dev/null +++ b/docs/twitter/2077241596869751029/thread_data.json @@ -0,0 +1,86 @@ +{ + "root_post_id": "2077241596869751029", + "posts": [ + { + "post_id": "2077224595858280506", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "One advantage of SAR (aka signed '>>') is that the shift-by operand HW uses only the 5|6 LSBs automatically. So if you have a mixed used control word, you don't have to mask out the MSBs. Can save an instruction.", + "timestamp": "2026-07-15 02:51:51", + "media_urls": [], + "reply_to_id": null, + "quote_of_id": null, + "metrics": { + "reply_count": 2, + "repost_count": 0, + "like_count": 9, + "view_count": 1694 + } + }, + { + "post_id": "2077225347049767246", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "Working through an idea of a single uber-instruction interpreted language for code generation. Meaning something that never misses the instruction cache and executes fully out of the micro-op cache. Fully data driven with a direct map 64k entry symbol table.", + "timestamp": "2026-07-15 02:54:50", + "media_urls": [], + "reply_to_id": "2077224595858280506", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 1, + "like_count": 12, + "view_count": 608 + } + }, + { + "post_id": "2077227411112870280", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "Borrows some ideas from SIMD GPU programming. Like instead of branching/predicating to avoid stores, just store to a discarded area (like a negative offset on the GPU, or a designated trash address on the CPU).", + "timestamp": "2026-07-15 03:03:02", + "media_urls": [], + "reply_to_id": "2077225347049767246", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 4, + "view_count": 375 + } + }, + { + "post_id": "2077234537302556898", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "Don't want exit condition logic in the infinite loop, so exit will have to be having the program store an exit value into a set address, and an external watchdog polling for exit at some sleep frequency.", + "timestamp": "2026-07-15 03:31:21", + "media_urls": [], + "reply_to_id": "2077227411112870280", + "quote_of_id": null, + "metrics": { + "reply_count": 1, + "repost_count": 0, + "like_count": 2, + "view_count": 469 + } + }, + { + "post_id": "2077241596869751029", + "author": "NOTimothyLottes", + "handle": "NOTimothyLottes", + "text": "SAR on a control word can in theory grab 3 values.\nSF (sign flag) is set to MSB bit\nCF (carry flag) is set to what shifts into bit -1\nand output\n\nThe SF and CF can be used for CMOVcc\nOutput can be used for another shift (after CMOVccs)", + "timestamp": "2026-07-15 03:59:24", + "media_urls": [], + "reply_to_id": "2077234537302556898", + "quote_of_id": null, + "metrics": { + "reply_count": 0, + "repost_count": 0, + "like_count": 2, + "view_count": 428 + } + } + ], + "source_url": "https://x.com/NOTimothyLottes/status/2077241596869751029" +} \ No newline at end of file