2661 lines
85 KiB
PHP
2661 lines
85 KiB
PHP
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if ~ defined AVX_512
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restore AVX_512 ; this ensures that symbol cannot be forward-referenced
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AVX_512 = 1
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include 'avx2.inc'
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element AVX_512.reg
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element AVX_512.r128 : AVX_512.reg + 16
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element AVX_512.r256 : AVX_512.reg + 32
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element AVX_512.r512 : AVX_512.reg + 64
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repeat 8, i:0
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element zmm#i? : AVX_512.r512 + i
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end repeat
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if defined xmm8
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repeat 16, i:16
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element xmm#i? : AVX_512.r128 + i
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element ymm#i? : AVX_512.r256 + i
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end repeat
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repeat 8+16, i:8
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element zmm#i? : AVX_512.r512 + i
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end repeat
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end if
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element AVX_512.maskreg
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repeat 8, i:0
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element k#i? : AVX_512.maskreg + i
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end repeat
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define x86.dqqword? :64
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define x86.zword? :64
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EVEX_AS_VEX = 0
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EVEX_W1 = 1 shl 15
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EVEX_REQUIRED = 1 shl 10
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EVEX_FORBIDDEN = 1 shl 2
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EVEX_VL = 1 shl 22
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AVX512VL = 0
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iterate context, @dest,@src,@src2,@aux
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namespace context
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define mask
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define evex_b
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define memsize
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define broadcast
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define rounding
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define visize
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calminstruction AVX_512.parse_operand#context operand
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call x86.parse_operand#context, operand
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check type = 'reg' & size = 1 & rm >= 4 & (~ defined x86.REX_FORBIDDEN | rm and x86.REX_FORBIDDEN)
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jyes invalid_operand
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check type = 'imm' & size = 0
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jno export_common
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check imm eq 1 elementof imm & 1 metadataof imm relativeto SSE.reg
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jyes xmm_register
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check imm eq 1 elementof imm & 1 metadataof imm relativeto AVX.reg
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jyes ymm_register
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check 1 metadataof (1 metadataof imm) relativeto AVX_512.reg & imm eq 1 elementof imm
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jyes xyzmm_register
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check imm eq 1 elementof imm & 1 metadataof imm relativeto AVX_512.maskreg
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jyes mask_register
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exit
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invalid_operand:
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err 'invalid operand'
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xmm_register:
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compute rm, 1 metadataof imm - SSE.reg
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compute size, 16
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jump export_mmreg
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ymm_register:
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compute rm, 1 metadataof imm - AVX.reg
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compute size, 32
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jump export_mmreg
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mask_register:
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compute rm, 1 metadataof imm - AVX_512.maskreg
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compute size, 8
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compute type, 'maskreg'
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jump export_reg
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xyzmm_register:
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compute rm, 1 metadataof imm - 1 elementof (1 metadataof imm)
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compute size, 1 metadataof (1 metadataof imm) - AVX_512.reg
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export_mmreg:
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compute type, 'mmreg'
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export_reg:
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compute mod, 11b
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export_common:
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compute mask, 0
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compute evex_b, 0
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compute memsize, 0
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end calminstruction
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calminstruction AVX_512.parse_k1z_operand#context operand
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local k1, z
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transform operand
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match operand {k1} { =z? }, operand
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jyes k1z
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match operand {k1}, operand
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jyes k1
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call AVX_512.parse_operand#context, operand
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exit
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k1z:
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compute z, 80h
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jump masked
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k1:
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compute z, 0
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masked:
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call AVX_512.parse_operand#context, operand
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check z & type = 'mem'
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jyes invalid_mask
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check k1 eq 1 elementof k1 & 1 metadataof k1 relativeto AVX_512.maskreg & 1 metadataof k1 - AVX_512.maskreg > 0
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jno invalid_mask
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compute mask, (1 metadataof k1 - AVX_512.maskreg) or z
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exit
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invalid_mask:
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err 'invalid mask'
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end calminstruction
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calminstruction AVX_512.parse_k1_operand#context operand
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local k1
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transform operand
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match operand {k1}, operand
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jyes k1
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call AVX_512.parse_operand#context, operand
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exit
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k1:
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call AVX_512.parse_operand#context, operand
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check k1 eq 1 elementof k1 & 1 metadataof k1 relativeto AVX_512.maskreg & 1 metadataof k1 - AVX_512.maskreg > 0
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jno invalid_mask
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compute mask, 1 metadataof k1 - AVX_512.maskreg
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exit
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invalid_mask:
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err 'invalid mask'
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end calminstruction
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calminstruction AVX_512.parse_bcst_operand#context operand,unit
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transform operand
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match operand {broadcast}, operand
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jyes mem_bcst
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call AVX_512.parse_operand#context, operand
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exit
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invalid_operand:
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err 'invalid operand'
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mem_bcst:
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call AVX_512.parse_operand#context, operand
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check type = 'mem'
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jno invalid_operand
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compute memsize, unit
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check memsize
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jyes implied_unit
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check size
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jno operand_size_not_specified
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compute memsize, size
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jump unit_ok
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operand_size_not_specified:
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err 'operand size not specified'
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exit
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implied_unit:
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check size and not memsize
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jno unit_ok
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err 'invalid operand size'
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exit
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unit_ok:
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match =1to2?, broadcast
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jyes bcst_2
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match =1to4?, broadcast
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jyes bcst_4
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match =1to8?, broadcast
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jyes bcst_8
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match =1to16?, broadcast
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jyes bcst_16
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err 'invalid broadcast'
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exit
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bcst_2:
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compute broadcast, 2
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jump bcst_ok
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bcst_4:
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compute broadcast, 4
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jump bcst_ok
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bcst_8:
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compute broadcast, 8
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jump bcst_ok
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bcst_16:
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compute broadcast, 16
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bcst_ok:
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compute size, memsize * broadcast
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compute evex_b, 1
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end calminstruction
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calminstruction AVX_512.parse_er#context operand,vsize:64
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check type = 'mem' | size <> vsize
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jyes invalid_operand
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match { =rn?-=sae? }, operand
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jyes rounding_0
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match { =rd?-=sae? }, operand
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jyes rounding_1
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match { =ru?-=sae? }, operand
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jyes rounding_2
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match { =rz?-=sae? }, operand
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jyes rounding_3
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invalid_operand:
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err 'invalid operand'
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exit
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rounding_0:
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compute rounding, 0
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jump rounding_ok
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rounding_1:
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compute rounding, 1
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jump rounding_ok
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rounding_2:
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compute rounding, 2
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jump rounding_ok
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rounding_3:
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compute rounding, 3
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jump rounding_ok
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rounding_ok:
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compute evex_b, 1
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end calminstruction
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calminstruction AVX_512.parse_sae#context operand
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check type = 'mem'
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jyes invalid_operand
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match { =sae? }, operand
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jno invalid_operand
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compute evex_b, 1
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compute rounding, -1
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exit
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invalid_operand:
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err 'invalid operand'
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end calminstruction
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calminstruction AVX_512.parse_vsib_operand#context operand
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local i, pre, suf
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compute segment_prefix, 0
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compute size, 0
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compute displacement_size, 0
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transform operand
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match pre suf, operand
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jno no_size_prefix
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transform pre, x86
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jno no_size_prefix
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match :size, pre
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jno no_size_prefix
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arrange operand, suf
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no_size_prefix:
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match [address], operand
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jyes memory_operand
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match =ptr? address, operand
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jyes memory_operand
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jump invalid_operand
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memory_operand:
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compute type, 'mem'
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match segment:address, address
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jno segment_prefix_ok
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check segment eq 1 elementof segment & 1 metadataof segment relativeto x86.sreg
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jno invalid_operand
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compute segment, 1 metadataof segment - x86.sreg
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check segment >= 4
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jyes segment_prefix_386
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compute segment_prefix, 26h + segment shl 3
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jump segment_prefix_ok
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segment_prefix_386:
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compute segment_prefix, 64h + segment-4
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segment_prefix_ok:
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match pre suf, address
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jno no_address_size_prefix
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transform pre, x86
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jno no_address_size_prefix
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match :pre, pre
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jno no_address_size_prefix
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arrange address, suf
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check pre = 4 | pre = 8
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jno invalid_address_size
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compute mode, pre shl 3
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no_address_size_prefix:
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compute mode, 0
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compute scale, 0
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compute index, 0
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compute base, 0
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compute auto_relative, 0
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check size
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jyes size_override
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compute size, sizeof address
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size_override:
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compute address, address
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compute base_registers, 0
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compute index_registers, 0
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compute i, 1
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extract_registers:
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check i > elementsof address
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jyes registers_extracted
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check i metadataof address relativeto SSE.reg | i metadataof address relativeto AVX.reg | 1 metadataof (i metadataof address) relativeto AVX_512.reg
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jyes index_term
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check i metadataof address relativeto x86.r32 | i metadataof address relativeto x86.r64
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jno next_term
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compute base_registers, base_registers + i elementof address * i scaleof address
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jump next_term
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index_term:
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compute index_registers, index_registers + i elementof address * i scaleof address
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next_term:
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compute i, i+1
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jump extract_registers
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registers_extracted:
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compute displacement, address - base_registers - index_registers
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compute auto_relative, 0
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check elementsof index_registers = 1
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jno invalid_address
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compute scale, 1 scaleof index_registers
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compute index, 0 scaleof (1 metadataof index_registers)
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check scale and (scale-1) | scale > 8
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jyes invalid_address
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check 1 metadataof index_registers relativeto SSE.reg
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jyes xmm_index
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check 1 metadataof index_registers relativeto AVX.reg
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jyes ymm_index
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compute visize, 1 metadataof (1 metadataof index_registers) - AVX_512.reg
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jump index_ok
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ymm_index:
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compute visize, 32
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jump index_ok
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xmm_index:
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compute visize, 16
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index_ok:
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compute rm, 4
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check elementsof base_registers = 1 & 1 scaleof base_registers = 1
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jyes base_and_index
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check elementsof base_registers = 0
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jno invalid_address
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compute base, 5
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compute displacement_size, 4
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compute mod, 0
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compute mode, x86.mode
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check mode > 16
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jyes ready
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compute mode, 32
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jump ready
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base_and_index:
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compute base, 0 scaleof (1 metadataof base_registers)
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check mode & mode <> 0 scaleof (1 metadataof (1 metadataof base_registers)) shl 3
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jyes invalid_address
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compute mode, 0 scaleof (1 metadataof (1 metadataof base_registers)) shl 3
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setup_displacement:
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check displacement relativeto 0
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jno displacement_32bit
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check displacement = 0 & rm and 111b <> 5 & (rm <> 4 | base and 111b <> 5)
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jyes displacement_empty
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check displacement < 80h & displacement >= -80h
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jyes displacement_8bit
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check displacement - 1 shl mode >= -80h & displacement < 1 shl mode
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jyes displacement_8bit_wrap
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displacement_32bit:
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compute displacement_size, 4
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compute mod, 2
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jump ready
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displacement_8bit_wrap:
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compute displacement, displacement - 1 shl mode
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displacement_8bit:
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compute displacement_size, 1
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compute mod, 1
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jump ready
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index_only:
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compute displacement_size, 4
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compute mod, 0
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jump ready
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displacement_empty:
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compute displacement_size, 0
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compute mod, 0
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ready:
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compute mask, 0
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compute evex_b, 0
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compute memsize, 0
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exit
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invalid_operand:
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err 'invalid operand'
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exit
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invalid_address:
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err 'invalid address'
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exit
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invalid_address_size:
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err 'invalid address size'
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exit
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end calminstruction
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calminstruction AVX_512.parse_k1_vsib_operand#context operand
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local k1
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transform operand
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match operand {k1}, operand
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jyes k1
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call AVX_512.parse_vsib_operand#context, operand
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exit
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k1:
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call AVX_512.parse_vsib_operand#context, operand
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check k1 eq 1 elementof k1 & 1 metadataof k1 relativeto AVX_512.maskreg & 1 metadataof k1 - AVX_512.maskreg > 0
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jno invalid_mask
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compute mask, 1 metadataof k1 - AVX_512.maskreg
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exit
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invalid_mask:
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err 'invalid mask'
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end calminstruction
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calminstruction AVX_512.store_instruction#context vsize*,vex_mpw*,evex_f*,opcode*,mask*,reg*,vreg:0,imm_size:0,immediate
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check segment_prefix
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jno segment_prefix_ok
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check mode = 64
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jyes segment_in_long_mode
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check mode = 16 & ( rm = 2 | rm = 3 | ( mod > 0 & rm = 6 ) )
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jyes ss_segment_default
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check mode = 32 & ( ( mod > 0 & rm = 5 ) | ( rm = 4 & base = 4 ) | ( mod > 0 & rm = 4 & base = 5 ) )
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jyes ss_segment_default
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ds_segment_default:
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check segment_prefix = 3Eh
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jyes segment_prefix_ok
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jump store_segment_prefix
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ss_segment_default:
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check segment_prefix = 36h
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jyes segment_prefix_ok
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jump store_segment_prefix
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segment_in_long_mode:
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check segment_prefix < 64h
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jyes segment_prefix_ok
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store_segment_prefix:
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emit 1, segment_prefix
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segment_prefix_ok:
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check mod <> 11b & mode <> x86.mode
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jno addressing_prefix_ok
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check mode = 64 | (mode = 16 & x86.mode = 64)
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jno store_addressing_prefix
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err 'illegal addressing mode'
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store_addressing_prefix:
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emit 1, 67h
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addressing_prefix_ok:
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compute evex, vex_mpw
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compute evex_flags, evex_f
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check evex_b
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jno evex_L'L
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compute evex, evex or evex_b shl 20
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evex_L'L:
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check mod = 11b & evex_b & rounding >= 0
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jyes evex_rounding
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check vsize = 64
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jyes evex_L'
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check evex_flags and EVEX_VL & AVX512VL = 0
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jno evex_L
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compute evex_flags, evex_flags or EVEX_FORBIDDEN
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evex_L:
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check vsize = 32
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jno evex_mask
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compute evex, evex or 1 shl 21
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jump evex_mask
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evex_L':
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compute evex, evex or 1 shl 22
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jump evex_mask
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evex_rounding:
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compute evex, evex or rounding shl 21
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evex_mask:
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check mask
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jno evex_X
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compute evex, evex or mask shl 16
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evex_X:
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check rm and 10000b | (mod <> 11b & mode > 16 & rm = 4 & index and 1000b)
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jno evex_B
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compute evex, evex or 1 shl 6
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evex_B:
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check rm and 1000b | (mod <> 11b & mode > 16 & rm = 4 & base and 1000b)
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jno evex_R'
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compute evex, evex or 1 shl 5
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evex_R':
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check reg and 10000b
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jno evex_R
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compute evex, evex or 1 shl 4
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evex_R:
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check reg and 1000b
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jno evex_V'
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compute evex, evex or 1 shl 7
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evex_V':
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check vreg and 10000b
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jno evex_vvvv
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compute evex, evex or 1 shl 19
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evex_vvvv:
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compute evex, evex or (vreg and 1111b) shl 11
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check x86.mode < 64 & evex and 00001000_01000000_11110000b
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jno allowed
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err 'instruction requires long mode'
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allowed:
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local evex_displacement_size, compressed_displacement
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check displacement_size
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jno no_displacement_compression
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compute displacement, displacement
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check (mode > 16 & rm = 5) | (mode = 16 & rm = 6)
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jyes no_displacement_compression
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check memsize
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jyes displacement_compression
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compute memsize, vsize
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displacement_compression:
|
|
check displacement relativeto 0 & displacement mod? memsize = 0
|
|
jno displacement_incompressible
|
|
compute compressed_displacement, displacement / memsize
|
|
check compressed_displacement < 80h & compressed_displacement >= -80h
|
|
jyes displacement_compressed
|
|
check compressed_displacement - 1 shl mode >= -80h & compressed_displacement < 1 shl mode
|
|
jno displacement_incompressible
|
|
compute compressed_displacement, compressed_displacement - 1 shl mode
|
|
displacement_compressed:
|
|
compute evex_displacement_size, 1
|
|
jump choose_prefix
|
|
displacement_incompressible:
|
|
compute evex_displacement_size, 4
|
|
check mode > 16
|
|
jyes choose_prefix
|
|
compute evex_displacement_size, 2
|
|
jump choose_prefix
|
|
no_displacement_compression:
|
|
compute evex_displacement_size, displacement_size
|
|
|
|
choose_prefix:
|
|
check evex_flags and EVEX_REQUIRED | evex and 11011111_00000000_00010000b | rm and 10000b
|
|
jyes evex_required
|
|
check ~ evex_flags and EVEX_FORBIDDEN & evex_displacement_size + 1 < displacement_size
|
|
jyes evex
|
|
jump vex
|
|
evex_required:
|
|
check evex_flags and EVEX_FORBIDDEN
|
|
jno evex
|
|
err 'invalid operand'
|
|
|
|
vex:
|
|
compute vex, evex and 11111011_11111111b or (evex and 1 shl 21) shr (21-10)
|
|
check vex and 10000000_01111111b <> 1
|
|
jyes vex_3byte
|
|
vex_2byte:
|
|
emit 1, 0C5h
|
|
emit 1, ((vex and 10000000b) or ((vex shr 8) and 1111111b)) xor 11111000b
|
|
jump evex_done
|
|
vex_3byte:
|
|
emit 1, 0C4h
|
|
emit 1, (vex and 11111111b) xor 11100000b
|
|
emit 1, (vex shr 8) xor 01111000b
|
|
jump evex_done
|
|
|
|
evex:
|
|
compute evex, evex or 1 shl 10
|
|
check evex_flags and EVEX_W1
|
|
jno evex_4byte
|
|
compute evex, evex or 1 shl 15
|
|
evex_4byte:
|
|
emit 4, 62h + (evex xor 00001000_01111000_11110000b) shl 8
|
|
check mod <> 11b & mod <> 0 & evex_displacement_size > 0
|
|
jno evex_done
|
|
compute displacement_size, evex_displacement_size
|
|
check evex_displacement_size = 1
|
|
jyes evex_compressed_displacement
|
|
compute mod, 2
|
|
jump evex_done
|
|
evex_compressed_displacement:
|
|
compute displacement, compressed_displacement
|
|
compute mod, 1
|
|
evex_done:
|
|
|
|
asm db opcode
|
|
emit 1, mod shl 6 + (reg and 111b) shl 3 + rm and 111b
|
|
|
|
check mod <> 11b & rm = 4 & mode <> 16
|
|
jno sib_ok
|
|
emit 1, (bsf scale) shl 6 + (index and 111b) shl 3 + base and 111b
|
|
sib_ok:
|
|
|
|
check displacement_size = 1
|
|
jyes displacement_8bit
|
|
check displacement_size = 2
|
|
jyes displacement_16bit
|
|
check displacement_size = 4 | displacement_size = 8
|
|
jno displacement_ok
|
|
|
|
check auto_relative
|
|
jno auto_relative_ok
|
|
check imm_size < 8
|
|
jyes adjust_auto_relative_displacement
|
|
compute displacement, displacement - ($ + 4 + 4)
|
|
jump auto_relative_ok
|
|
adjust_auto_relative_displacement:
|
|
compute displacement, displacement - ($ + 4 + imm_size)
|
|
auto_relative_ok:
|
|
|
|
check mode = 64 & displacement relativeto 0
|
|
jno displacement_ready
|
|
check displacement - 1 shl 64 >= -80000000h & displacement < 1 shl 64
|
|
jyes adjust_displacement_wrap
|
|
check displacement >= -80000000h & displacement < 80000000h
|
|
jyes displacement_ready
|
|
err 'address value out of signed range'
|
|
adjust_displacement_wrap:
|
|
compute displacement, displacement - 1 shl 64
|
|
displacement_ready:
|
|
|
|
asm dd displacement
|
|
|
|
jump displacement_ok
|
|
displacement_16bit:
|
|
asm dw displacement
|
|
jump displacement_ok
|
|
displacement_8bit:
|
|
emit 1, displacement
|
|
displacement_ok:
|
|
|
|
check imm_size = 1
|
|
jyes immediate_8bit
|
|
check imm_size = 2
|
|
jyes immediate_16bit
|
|
check imm_size = 4
|
|
jyes immediate_32bit
|
|
check imm_size = 8
|
|
jno immediate_ok
|
|
call x86.simm32, immediate
|
|
jump immediate_ok
|
|
immediate_32bit:
|
|
compute imm, +immediate
|
|
asm dd imm
|
|
jump immediate_ok
|
|
immediate_16bit:
|
|
compute imm, +immediate
|
|
asm dw imm
|
|
jump immediate_ok
|
|
immediate_8bit:
|
|
compute imm, +immediate
|
|
emit 1, imm
|
|
immediate_ok:
|
|
|
|
end calminstruction
|
|
|
|
end namespace
|
|
|
|
end iterate
|
|
|
|
macro AVX_512.basic_instruction_bcst_er vex_mpw,evex_f,opcode,unit,dest,src,src_er&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
match src2=,er, src_er
|
|
AVX_512.parse_operand@src2 src2
|
|
AVX_512.parse_er@src2 er
|
|
else
|
|
AVX_512.parse_bcst_operand@src2 src_er,unit
|
|
end match
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if @src.size <> @dest.size | @src2.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.basic_instruction_bcst_sae vex_mpw,evex_f,opcode,unit,dest,src,src_sae&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
match src2=,sae, src_sae
|
|
AVX_512.parse_operand@src2 src2
|
|
AVX_512.parse_sae@src2 sae
|
|
else
|
|
AVX_512.parse_bcst_operand@src2 src_sae,unit
|
|
end match
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if @src.size <> @dest.size | @src2.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.basic_instruction_bcst_sae_imm8 vex_mpw,evex_f,opcode,unit,dest,src,src2,aux&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_bcst_operand@src2 src2,unit
|
|
match sae=,imm, aux
|
|
AVX_512.parse_sae@src2 sae
|
|
x86.parse_operand@aux imm
|
|
else
|
|
x86.parse_operand@aux aux
|
|
end match
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'
|
|
if @src.size <> @dest.size | @src2.size and not @dest.size | @aux.size and not 1
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.basic_instruction_bcst vex_mpw,evex_f,opcode,unit,dest,src,src2
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_bcst_operand@src2 src2,unit
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if @src.size <> @dest.size | @src2.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.basic_instruction_bcst_imm8 vex_mpw,evex_f,opcode,unit,dest,src,src2,aux
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_bcst_operand@src2 src2,unit
|
|
x86.parse_operand@aux aux
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'
|
|
if @aux.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src.size <> @dest.size | @src2.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.basic_instruction_er vex_mpw,evex_f,opcode,unit,dest,src,src_er&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
match src2=,er, src_er
|
|
AVX_512.parse_operand@src2 src2
|
|
AVX_512.parse_er@src2 er,(unit-1) and not 15 + 16
|
|
else
|
|
AVX_512.parse_operand@src2 src_er
|
|
end match
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src2.type = 'mem' & @src2.size and not unit) )
|
|
err 'invalid operand size'
|
|
else if @dest.size <> @src.size | (@src2.size and not @dest.size & (unit = 0 | @src2.type = 'mmreg'))
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@src2.memsize = unit
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.basic_instruction_sae vex_mpw,evex_f,opcode,unit,dest,src,src_sae&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
match src2=,sae, src_sae
|
|
AVX_512.parse_operand@src2 src2
|
|
AVX_512.parse_sae@src2 sae
|
|
else
|
|
AVX_512.parse_operand@src2 src_sae
|
|
end match
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src2.type = 'mem' & @src2.size and not unit) )
|
|
err 'invalid operand size'
|
|
else if @dest.size <> @src.size | (@src2.size and not @dest.size & (unit = 0 | @src2.type = 'mmreg'))
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@src2.memsize = unit
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.basic_instruction_sae_imm8 vex_mpw,evex_f,opcode,unit,dest,src,src2,aux&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_operand@src2 src2
|
|
match sae=,imm, aux
|
|
AVX_512.parse_sae@src2 sae
|
|
x86.parse_operand@aux imm
|
|
else
|
|
x86.parse_operand@aux aux
|
|
end match
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'
|
|
if ( unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src2.type = 'mem' & @src2.size and not unit) ) ) | @aux.size and not 1
|
|
err 'invalid operand size'
|
|
else if @dest.size <> @src.size | (@src2.size and not @dest.size & (unit = 0 | @src2.type = 'mmreg'))
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@src2.memsize = unit
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.basic_instruction vex_mpw,evex_f,opcode,unit,dest,src,src2
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_operand@src2 src2
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src2.type = 'mem' & @src2.size and not unit) )
|
|
err 'invalid operand size'
|
|
else if @dest.size <> @src.size | (@src2.size and not @dest.size & (unit = 0 | @src2.type = 'mmreg'))
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@src2.memsize = unit
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.basic_instruction_imm8 vex_mpw,evex_f,opcode,unit,dest,src,src2,aux&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_operand@src2 src2
|
|
x86.parse_operand@aux aux
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'
|
|
if ( unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src2.type = 'mem' & @src2.size and not unit) ) ) | @aux.size and not 1
|
|
err 'invalid operand size'
|
|
else if @dest.size <> @src.size | (@src2.size and not @dest.size & (unit = 0 | @src2.type = 'mmreg'))
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@src2.memsize = unit
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.single_source_instruction_bcst_er vex_mpw,evex_f,opcode,unit,dest,src_er&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
match src=,er, src_er
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_er@src er
|
|
else
|
|
AVX_512.parse_bcst_operand@src src_er,unit
|
|
end match
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.single_source_instruction_bcst_sae vex_mpw,evex_f,opcode,unit,dest,src_sae&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
match src=,sae, src_sae
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_sae@src sae
|
|
else
|
|
AVX_512.parse_bcst_operand@src src_sae,unit
|
|
end match
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.single_source_instruction_bcst_sae_imm8 vex_mpw,evex_f,opcode,unit,dest,src,aux&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_bcst_operand@src src,unit
|
|
match sae=,imm, aux
|
|
AVX_512.parse_sae@src sae
|
|
x86.parse_operand@aux imm
|
|
else
|
|
x86.parse_operand@aux aux
|
|
end match
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @aux.type = 'imm'
|
|
if @aux.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm,,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.single_source_instruction_bcst vex_mpw,evex_f,opcode,unit,dest,src&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_bcst_operand@src src,unit
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro AVX_512.single_source_instruction vex_mpw,evex_f,opcode,unit,dest,src
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src.type = 'mem' & @src.size and not unit) )
|
|
err 'invalid operand size'
|
|
else if @src.size and not @dest.size & (unit = 0 | @src.type = 'mmreg')
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@src.memsize = unit
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
iterate <instr,opcode>, add,58h, mul,59h, sub,5Ch, div,5Eh
|
|
|
|
macro v#instr#pd? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst_er VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
macro v#instr#ps? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst_er VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2
|
|
end macro
|
|
|
|
macro v#instr#sd? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_er VEX_F2_0F_W0,EVEX_W1,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
macro v#instr#ss? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_er VEX_F3_0F_W0,EVEX_AS_VEX,opcode,4,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, min,5Dh, max,5Fh
|
|
|
|
macro v#instr#pd? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst_sae VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
macro v#instr#ps? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst_sae VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2
|
|
end macro
|
|
|
|
macro v#instr#sd? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_sae VEX_F2_0F_W0,EVEX_W1,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
macro v#instr#ss? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_sae VEX_F3_0F_W0,EVEX_AS_VEX,opcode,4,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, unpckh,15h, unpckl,14h
|
|
|
|
macro v#instr#pd? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
macro v#instr#ps? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
macro vsqrtpd? dest*,src*&
|
|
AVX_512.single_source_instruction_bcst_er VEX_66_0F_W0,EVEX_W1+EVEX_VL,51h,8,dest,src
|
|
end macro
|
|
|
|
macro vsqrtps? dest*,src*&
|
|
AVX_512.single_source_instruction_bcst_er VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,51h,4,dest,src
|
|
end macro
|
|
|
|
macro vsqrtsd? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_er VEX_F2_0F_W0,EVEX_W1,51h,8,dest,src,src2
|
|
end macro
|
|
|
|
macro vsqrtss? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_er VEX_F3_0F_W0,EVEX_AS_VEX,51h,4,dest,src,src2
|
|
end macro
|
|
|
|
macro vshufpd? dest*,src*,src2*,aux*&
|
|
AVX_512.basic_instruction_bcst_imm8 VEX_66_0F_W0,EVEX_W1+EVEX_VL,0C6h,8,dest,src,src2,aux
|
|
end macro
|
|
|
|
macro vshufps? dest*,src*,src2*,aux*&
|
|
AVX_512.basic_instruction_bcst_imm8 VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,0C6h,4,dest,src,src2,aux
|
|
end macro
|
|
|
|
macro vbroadcastss? dest*,src*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')
|
|
if (@src.type = 'mmreg' & @src.size <> 16) | (@src.type = 'mem' & @src.size and not 4)
|
|
err 'invalid operand size'
|
|
end if
|
|
@src2.memsize = 4
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,18h,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro vbroadcastsd? dest*,src*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')
|
|
if @dest.size = 16 | (@src.type = 'mmreg' & @src.size <> 16) | (@src.type = 'mem' & @src.size and not 8)
|
|
err 'invalid operand size'
|
|
end if
|
|
@src.memsize = 8
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F38_W0,EVEX_W1+EVEX_VL,19h,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
iterate <instr,opcode,opcode_g,msize>, vpbroadcastd,58h,7Ch,4, vpbroadcastq,59h,7Ch,8
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')
|
|
if (@src.type='mmreg' & @src.size <> 16) | (@src.type = 'mem' & @src.size and not msize)
|
|
err 'invalid operand size'
|
|
end if
|
|
@src.memsize = msize
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX,opcode,@dest.mask,@dest.rm
|
|
else if @dest.type = 'mmreg' & @src.type = 'reg'
|
|
if @src.size <> msize & (@src.size <> 4 | msize = 8)
|
|
err 'invalid operand size'
|
|
end if
|
|
@src.memsize = msize
|
|
if msize = 8
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode_g,@dest.mask,@dest.rm
|
|
else
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode_g,@dest.mask,@dest.rm
|
|
end if
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,opcode,msize>, vbroadcastf32x4,VEX_66_0F38_W0,1Ah,16, vbroadcastf64x4,VEX_66_0F38_W1,1Bh,32, \
|
|
vbroadcasti32x4,VEX_66_0F38_W0,5Ah,16, vbroadcasti64x4,VEX_66_0F38_W1,5Bh,32
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & @src.type = 'mem'
|
|
if @dest.size <= msize | @src.size and not msize
|
|
err 'invalid operand size'
|
|
end if
|
|
@src.memsize = msize
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,opcode,unit>, vshuff32x4,VEX_66_0F3A_W0,23h,4, vshuff64x2,VEX_66_0F3A_W1,23h,4, \
|
|
vshufi32x4,VEX_66_0F3A_W0,43h,4, vshufi64x2,VEX_66_0F3A_W1,43h,4
|
|
|
|
macro instr? dest*,src*,src2*,aux*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_bcst_operand@src2 src2,unit
|
|
x86.parse_operand@aux aux
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'
|
|
if @dest.size < 32 | @aux.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src.size <> @dest.size | @src2.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
macro vextractps? dest*,src*,aux*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
x86.parse_operand@aux aux
|
|
if (@dest.type = 'reg' | @dest.type = 'mem') & @src.type = 'mmreg' & @aux.type = 'imm'
|
|
if @dest.size and not 4 | @src.size <> 16 | @aux.size and not 1
|
|
err 'invalid operand size'
|
|
end if
|
|
@dest.memsize = 4
|
|
AVX_512.store_instruction@dest 16,VEX_66_0F3A_W0,EVEX_AS_VEX,17h,0,@src.rm,,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro vinsertps? dest*,src*,src2*,aux*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_operand@src2 src2
|
|
x86.parse_operand@aux aux
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mmreg' | @src2.type = 'mem') & @aux.type = 'imm'
|
|
if @dest.size <> 16 | @src.size <> 16 | (@src2.type = 'mmreg' & @src2.size <> 16) | (@src2.type = 'mem' & @src2.size and not 4) | @aux.size and not 1
|
|
err 'invalid operand size'
|
|
end if
|
|
@src2.memsize = 4
|
|
AVX_512.store_instruction@src2 16,VEX_66_0F3A_W0,EVEX_AS_VEX,21h,0,@dest.rm,@src.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
iterate <instr,vex_mpw,opcode,msize>, vextractf32x4,VEX_66_0F3A_W0,19h,16, vextractf64x4,VEX_66_0F3A_W1,1Bh,32, \
|
|
vextracti32x4,VEX_66_0F3A_W0,39h,16, vextracti64x4,VEX_66_0F3A_W1,3Bh,32
|
|
|
|
macro instr? dest*,src*,aux*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
x86.parse_operand@aux aux
|
|
if (@dest.type = 'mmreg' | @dest.type = 'mem') & @src.type = 'mmreg' & @aux.type = 'imm'
|
|
if @dest.size and not msize | @src.size <= msize | @aux.size and not 1
|
|
err 'invalid operand size'
|
|
end if
|
|
@dest.memsize = msize
|
|
AVX_512.store_instruction@dest @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@src.rm,,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,opcode,msize>, vinsertf32x4,VEX_66_0F3A_W0,18h,16, vinsertf64x4,VEX_66_0F3A_W1,1Ah,32, \
|
|
vinserti32x4,VEX_66_0F3A_W0,38h,16, vinserti64x4,VEX_66_0F3A_W1,3Ah,32
|
|
|
|
macro instr? dest*,src*,src2*,aux*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_operand@src2 src2
|
|
x86.parse_operand@aux aux
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mmreg' | @src2.type = 'mem') & @aux.type = 'imm'
|
|
if @dest.size <= msize | @src.size <= msize | @src2.size and not msize | @aux.size and not 1
|
|
err 'invalid operand size'
|
|
end if
|
|
@src2.memsize = msize
|
|
AVX_512.store_instruction@src2 @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,evex_mpw,unit>, vcmpps,VEX_0F_W0,VEX_0F_W0,4, vcmppd,VEX_66_0F_W0,VEX_66_0F_W1,8
|
|
|
|
macro instr? dest*,src*,src2*,aux*&
|
|
AVX_512.parse_k1_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_bcst_operand@src2 src2,unit
|
|
match sae=,imm, aux
|
|
AVX_512.parse_sae@src2 sae
|
|
x86.parse_operand@aux imm
|
|
else
|
|
x86.parse_operand@aux aux
|
|
end match
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'
|
|
if @aux.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src.size <> @dest.size | @src2.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @src.size,vex_mpw,EVEX_FORBIDDEN,0C2h,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'
|
|
if @aux.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src2.size and not @src.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @src.size,evex_mpw,EVEX_REQUIRED+EVEX_VL,0C2h,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,evex_mpw,unit>, vcmpss,VEX_F3_0F_W0,VEX_F3_0F_W0,4, vcmpsd,VEX_F2_0F_W0,VEX_F2_0F_W1,8
|
|
|
|
macro instr? dest*,src*,src2*,aux*&
|
|
AVX_512.parse_k1_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_operand@src2 src2
|
|
match sae=,imm, aux
|
|
AVX_512.parse_sae@src2 sae
|
|
x86.parse_operand@aux imm
|
|
else
|
|
x86.parse_operand@aux aux
|
|
end match
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'
|
|
if @dest.size <> 16 | (@src2.type = 'mem' & @src2.size and not unit)
|
|
err 'invalid operand size'
|
|
else if @dest.size <> @src.size | (@src2.type = 'mmreg' & @src2.size <> @dest.size)
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@src2.memsize = unit
|
|
AVX_512.store_instruction@src2 @src.size,vex_mpw,EVEX_FORBIDDEN,0C2h,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'
|
|
if @src.size <> 16 | (@src2.type = 'mem' & @src2.size and not unit) | @aux.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src2.type = 'mmreg' & @src2.size <> @src.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@src2.memsize = unit
|
|
AVX_512.store_instruction@src2 @src.size,evex_mpw,EVEX_REQUIRED,0C2h,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <cond,code>, eq,0, lt,1, le,2, unord,3, neq,4, nlt,5, nle,6, ord,7, \
|
|
eq_uq,8, nge,9, ngt,0Ah, false,0Bh, neq_qq,0Ch, ge,0Dh, gt,0Eh, true,0Fh, \
|
|
eq_os,10h, lt_oq,11h, le_oq,12h, unord_s,13h, neq_us,14h, nlt_uq,15h, nle_uq,16h, ord_s,17h, \
|
|
eq_us,18h, nge_uq,19h, ngt_uq,1Ah, false_os,1Bh, neq_os,1Ch, ge_oq,1Dh, gt_oq,1Eh, true_us,1Fh
|
|
|
|
macro vcmp#cond#pd? dest*,src*,src2*&
|
|
vcmppd dest,src,src2,code
|
|
end macro
|
|
|
|
macro vcmp#cond#ps? dest*,src*,src2*&
|
|
vcmpps dest,src,src2,code
|
|
end macro
|
|
|
|
macro vcmp#cond#sd? dest*,src*,src2*&
|
|
vcmpsd dest,src,src2,code
|
|
end macro
|
|
|
|
macro vcmp#cond#ss? dest*,src*,src2*&
|
|
vcmpss dest,src,src2,code
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,evex_f,opcode,unit>, vcomiss,VEX_0F_W0,EVEX_AS_VEX,2Fh,4, vcomisd,VEX_66_0F_W0,EVEX_W1,2Fh,8, vucomiss,VEX_0F_W0,EVEX_AS_VEX,2Eh,4, vucomisd,VEX_66_0F_W0,EVEX_W1,2Eh,8
|
|
|
|
macro instr? dest*,src_sae*&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
match src=,sae, src_sae
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_sae@src sae
|
|
else
|
|
AVX_512.parse_operand@src src_sae
|
|
end match
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if unit & ( @dest.size <> (unit-1) and not 15 + 16 | (@src.type = 'mem' & @src.size and not unit) )
|
|
err 'invalid operand size'
|
|
else if @src.size and not @dest.size & (unit = 0 | @src.type = 'mmreg')
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@src.memsize = unit
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, kandw,41h, kandnw,42h, knotw,44h, korw,45h, kxnorw,46h, kxorw,47h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_operand@src2 src2
|
|
if @dest.type = 'maskreg' & @src.type = 'maskreg' & @src2.type = 'maskreg'
|
|
AVX.store_instruction@src2 32,VEX_0F_W0,opcode,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, knotw,44h, kortestw,98h
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'maskreg' & @src.type = 'maskreg'
|
|
AVX.store_instruction@src 16,VEX_0F_W0,opcode,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
macro kmovw? dest*,src*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'maskreg' & (@src.type = 'maskreg' | @src.type = 'mem')
|
|
if @src.type = 'mem' & @src.size and not 2
|
|
err 'invalid operand size'
|
|
end if
|
|
AVX.store_instruction@src 16,VEX_0F_W0,90h,@dest.rm
|
|
else if @dest.type = 'mem' & @src.type = 'maskreg'
|
|
if @dest.size and not 2
|
|
err 'invalid operand size'
|
|
end if
|
|
AVX.store_instruction@dest 16,VEX_0F_W0,91h,@src.rm
|
|
else if @dest.type = 'maskreg' & @src.type = 'reg'
|
|
if @src.size <> 4
|
|
err 'invalid operand size'
|
|
end if
|
|
AVX.store_instruction@src 16,VEX_0F_W0,92h,@dest.rm
|
|
else if @dest.type = 'reg' & @src.type = 'maskreg'
|
|
if @dest.size <> 4
|
|
err 'invalid operand size'
|
|
end if
|
|
AVX.store_instruction@src 16,VEX_0F_W0,93h,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
iterate <instr,vex_mpw,opcode>, kshiftrw,VEX_66_0F3A_W1,30h, kshiftlw,VEX_66_0F3A_W1,32h
|
|
|
|
macro instr? dest*,src*,aux*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
x86.parse_operand@aux aux
|
|
if @dest.type = 'maskreg' & @src.type = 'maskreg' & @aux.type = 'imm'
|
|
if @aux.size and not 1
|
|
err 'invalid operand size'
|
|
end if
|
|
AVX.store_instruction@src 16,vex_mpw,opcode,@dest.rm,,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
macro kunpckbw? dest*,src*,src2*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_operand@src2 src2
|
|
if @dest.type = 'maskreg' & @src.type = 'maskreg' & @src2.type = 'maskreg'
|
|
AVX.store_instruction@src2 32,VEX_66_0F_W0,4Bh,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
iterate <instr,evex_f,opcode>, vcvtdq2pd,EVEX_AS_VEX+EVEX_VL,0E6h, vcvtudq2pd,EVEX_REQUIRED+EVEX_VL,7Ah
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_bcst_operand@src src,4
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if (@src.type = 'mem' & @src.size and not (@dest.size shr 1)) | (@src.type = 'mmreg' & (@dest.size shr 1 - 1) and not 15 + 16 <> @src.size)
|
|
err 'invalid operand size'
|
|
end if
|
|
if @src.memsize = 0
|
|
@src.memsize = @dest.size shr 1
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,VEX_F3_0F_W0,evex_f,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,evex_f,opcode>, vcvtpd2dq,VEX_F2_0F_W0,EVEX_W1+EVEX_VL,0E6h, vcvtpd2ps,VEX_66_0F_W0,EVEX_W1+EVEX_VL,5Ah, vcvtpd2udq,VEX_0F_W1,EVEX_REQUIRED+EVEX_VL,79h
|
|
|
|
macro instr? dest*,src_er*&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
match src=,er, src_er
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_er@src er
|
|
else
|
|
AVX_512.parse_bcst_operand@src src_er,8
|
|
end match
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if @src.size = 0
|
|
if @dest.size = 16
|
|
err 'operand size not specified'
|
|
else
|
|
@src.size = 64
|
|
end if
|
|
end if
|
|
if (@src.size shr 1 - 1) and not 15 + 16 <> @dest.size | @src.size > 64
|
|
err 'invalid operand size'
|
|
end if
|
|
AVX_512.store_instruction@src @src.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,evex_f,opcode>, vcvtps2pd,VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,5Ah
|
|
|
|
macro instr? dest*,src_sae*&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
match src=,sae, src_sae
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_sae@src sae
|
|
else
|
|
AVX_512.parse_bcst_operand@src src_sae,4
|
|
end match
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if (@src.type = 'mem' & @src.size and not (@dest.size shr 1)) | (@src.type = 'mmreg' & (@dest.size shr 1 - 1) and not 15 + 16 <> @src.size)
|
|
err 'invalid operand size'
|
|
end if
|
|
if @src.memsize = 0
|
|
@src.memsize = @dest.size shr 1
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,evex_f,opcode>, vcvttpd2dq,VEX_66_0F_W0,EVEX_W1+EVEX_VL,0E6h, vcvttpd2udq,VEX_0F_W1,EVEX_REQUIRED+EVEX_VL,78h
|
|
|
|
macro instr? dest*,src_sae*&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
match src=,sae, src_sae
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_sae@src sae
|
|
else
|
|
AVX_512.parse_bcst_operand@src src_sae,8
|
|
end match
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if @src.size = 0
|
|
if @dest.size = 16
|
|
err 'operand size not specified'
|
|
else
|
|
@src.size = 64
|
|
end if
|
|
end if
|
|
if (@src.size shr 1 - 1) and not 15 + 16 <> @dest.size | @src.size > 64
|
|
err 'invalid operand size'
|
|
end if
|
|
AVX_512.store_instruction@src @src.size,vex_mpw,evex_f,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,evex_f,opcode>, vcvtdq2ps,VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,5Bh, vcvtudq2ps,VEX_F2_0F_W0,EVEX_REQUIRED+EVEX_VL,7Ah, \
|
|
vcvtps2dq,VEX_66_0F_W0,EVEX_AS_VEX+EVEX_VL,5Bh, vcvtps2udq,VEX_0F_W0,EVEX_REQUIRED+EVEX_VL,79h
|
|
|
|
macro instr? dest*,src*&
|
|
AVX_512.single_source_instruction_bcst_er vex_mpw,evex_f,opcode,4,dest,src
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
|
|
iterate <instr,vex_mpw,evex_f,opcode>, vcvttps2dq,VEX_F3_0F_W0,EVEX_AS_VEX+EVEX_VL,5Bh, vcvttps2udq,VEX_0F_W0,EVEX_REQUIRED+EVEX_VL,78h
|
|
|
|
macro instr? dest*,src*&
|
|
AVX_512.single_source_instruction_bcst_sae vex_mpw,evex_f,opcode,4,dest,src
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
macro vcvtph2ps? dest*,src_sae*&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
match src=,sae, src_sae
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_sae@src sae
|
|
else
|
|
AVX_512.parse_operand@src src_sae
|
|
end match
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if (@src.type = 'mem' & @src.size and not (@dest.size shr 1)) | (@src.type = 'mmreg' & (@dest.size shr 1 - 1) and not 15 + 16 <> @src.size)
|
|
err 'invalid operand size'
|
|
end if
|
|
if @src.memsize = 0
|
|
@src.memsize = @dest.size shr 1
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,13h,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro vcvtps2ph? dest*,src*,aux*&
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
match sae=,imm, aux
|
|
AVX_512.parse_sae@dest sae
|
|
x86.parse_operand@aux imm
|
|
else
|
|
x86.parse_operand@aux aux
|
|
end match
|
|
if (@dest.type = 'mem' | @dest.type = 'mmreg') & @src.type = 'mmreg'
|
|
if (@dest.type = 'mem' & @dest.size and not (@src.size shr 1)) | (@dest.type = 'mmreg' & (@src.size shr 1 - 1) and not 15 + 16 <> @dest.size)
|
|
err 'invalid operand size'
|
|
end if
|
|
if @dest.memsize = 0
|
|
@dest.memsize = @src.size shr 1
|
|
end if
|
|
AVX_512.store_instruction@dest @src.size,VEX_66_0F3A_W0,EVEX_AS_VEX+EVEX_VL,1Dh,@dest.mask,@src.rm,,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
iterate <instr,vex_mp,evex_f,opcode,msize>, vcvtsd2si,VEX_F2_0F,EVEX_AS_VEX,2Dh,8, vcvtss2si,VEX_F3_0F,EVEX_AS_VEX,2Dh,4, \
|
|
vcvtsd2usi,VEX_F2_0F,EVEX_REQUIRED,79h,8, vcvtss2usi,VEX_F3_0F,EVEX_REQUIRED,79h,4
|
|
|
|
macro instr? dest*,src_er*&
|
|
x86.parse_operand@dest dest
|
|
match src=,er, src_er
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_er@src er,16
|
|
else
|
|
AVX_512.parse_operand@src src_er
|
|
end match
|
|
if @dest.type = 'reg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if (@dest.size <> 4 & @dest.size <> 8) | (@src.type = 'mem' & @src.size and not msize) | (@src.type = 'mmreg' & @src.size <> 16)
|
|
err 'invalid operand size'
|
|
end if
|
|
if @dest.size = 8
|
|
if x86.mode < 64
|
|
err 'instruction requires long mode'
|
|
end if
|
|
AVX_512.store_instruction@src 16,vex_mp#_W1,evex_f,opcode,0,@dest.rm
|
|
else
|
|
AVX_512.store_instruction@src 16,vex_mp#_W0,evex_f,opcode,0,@dest.rm
|
|
end if
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mp,evex_f,opcode,msize>, vcvttsd2si,VEX_F2_0F,EVEX_AS_VEX,2Ch,8, vcvttss2si,VEX_F3_0F,EVEX_AS_VEX,2Ch,4, \
|
|
vcvttsd2usi,VEX_F2_0F,EVEX_REQUIRED,78h,8, vcvttss2usi,VEX_F3_0F,EVEX_REQUIRED,78h,4
|
|
|
|
macro instr? dest*,src_sae*&
|
|
x86.parse_operand@dest dest
|
|
match src=,sae, src_sae
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_sae@src sae
|
|
else
|
|
AVX_512.parse_operand@src src_sae
|
|
end match
|
|
if @dest.type = 'reg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
if (@dest.size <> 4 & @dest.size <> 8) | (@src.type = 'mem' & @src.size and not msize) | (@src.type = 'mmreg' & @src.size <> 16)
|
|
err 'invalid operand size'
|
|
end if
|
|
if @dest.size = 8
|
|
if x86.mode < 64
|
|
err 'instruction requires long mode'
|
|
end if
|
|
AVX_512.store_instruction@src 16,vex_mp#_W1,evex_f,opcode,0,@dest.rm
|
|
else
|
|
AVX_512.store_instruction@src 16,vex_mp#_W0,evex_f,opcode,0,@dest.rm
|
|
end if
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
macro vcvtsd2ss? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_er VEX_F2_0F_W0,EVEX_W1,5Ah,8,dest,src,src2
|
|
end macro
|
|
|
|
macro vcvtss2sd? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_sae VEX_F3_0F_W0,EVEX_AS_VEX,5Ah,4,dest,src,src2
|
|
end macro
|
|
|
|
iterate <instr,evex_f,opcode>, vcvtsi2sd,EVEX_AS_VEX,2Ah, vcvtusi2sd,EVEX_REQUIRED,7Bh
|
|
|
|
macro instr? dest*,src*,src_er*&
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
match src2=,er, src_er
|
|
AVX_512.parse_operand@src2 src2
|
|
AVX_512.parse_er@src2 er,8
|
|
else
|
|
AVX_512.parse_operand@src2 src_er
|
|
end match
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'reg' | @src2.type = 'mem')
|
|
if @src.size = 0
|
|
err ' operand size not specified'
|
|
else if @dest.size <> 16 | @src.size <> 16 | (@src2.size <> 4 & @src2.size <> 8)
|
|
err 'invalid operand size'
|
|
end if
|
|
if @src2.size = 8
|
|
if x86.mode < 64
|
|
err 'instruction requires long mode'
|
|
end if
|
|
AVX_512.store_instruction@src2 16,VEX_F2_0F_W1,evex_f,opcode,0,@dest.rm,@src.rm
|
|
else
|
|
AVX_512.store_instruction@src2 16,VEX_F2_0F_W0,evex_f,opcode,0,@dest.rm,@src.rm
|
|
end if
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,evex_f,opcode>, vcvtsi2ss,EVEX_AS_VEX,2Ah, vcvtusi2ss,EVEX_REQUIRED,7Bh
|
|
|
|
macro instr? dest*,src*,src_er*&
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
match src2=,er, src_er
|
|
AVX_512.parse_operand@src2 src2
|
|
AVX_512.parse_er@src2 er,@src2.size
|
|
else
|
|
AVX_512.parse_operand@src2 src_er
|
|
end match
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'reg' | @src2.type = 'mem')
|
|
if @src.size = 0
|
|
err ' operand size not specified'
|
|
else if @dest.size <> 16 | @src.size <> 16 | (@src2.size <> 4 & @src2.size <> 8)
|
|
err 'invalid operand size'
|
|
end if
|
|
if @src2.size = 8
|
|
if x86.mode < 64
|
|
err 'instruction requires long mode'
|
|
end if
|
|
AVX_512.store_instruction@src2 16,VEX_F3_0F_W1,evex_f,opcode,0,@dest.rm,@src.rm
|
|
else
|
|
AVX_512.store_instruction@src2 16,VEX_F3_0F_W0,evex_f,opcode,0,@dest.rm,@src.rm
|
|
end if
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,evex_f,opcode_rm,opcode_mr>, vmovapd,VEX_66_0F_W0,EVEX_W1+EVEX_VL,28h,29h, vmovaps,VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,28h,29h, \
|
|
vmovupd,VEX_66_0F_W0,EVEX_W1+EVEX_VL,10h,11h, vmovups,VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,10h,11h, \
|
|
vmovdqa32,VEX_66_0F_W0,EVEX_REQUIRED+EVEX_VL,6Fh,7Fh, vmovdqa64,VEX_66_0F_W1,EVEX_REQUIRED+EVEX_VL,6Fh,7Fh, \
|
|
vmovdqu32,VEX_F3_0F_W0,EVEX_REQUIRED+EVEX_VL,6Fh,7Fh, vmovdqu64,VEX_F3_0F_W1,EVEX_REQUIRED+EVEX_VL,6Fh,7Fh
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')
|
|
if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,evex_f,opcode_rm,@dest.mask,@dest.rm
|
|
else if @dest.type = 'mem' & @src.type = 'mmreg'
|
|
if @dest.size and not @src.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@dest @src.size,vex_mpw,evex_f,opcode_mr,@dest.mask,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
macro vmovd? dest*,src*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & (@src.type = 'reg' | @src.type = 'mem')
|
|
if @dest.size <> 16 | @src.size and not 4
|
|
err 'invalid operand size'
|
|
end if
|
|
@src.memsize = 4
|
|
AVX_512.store_instruction@src 16,VEX_66_0F_W0,EVEX_AS_VEX,6Eh,0,@dest.rm
|
|
else if (@dest.type = 'reg' | @dest.type = 'mem') & @src.type = 'mmreg'
|
|
if @dest.size and not 4 | @src.size <> 16
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@dest.memsize = 4
|
|
AVX_512.store_instruction@dest 16,VEX_66_0F_W0,EVEX_AS_VEX,7Eh,0,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro vmovq? dest*,src*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')
|
|
if @dest.size <> 16 | (@src.type = 'mmreg' & @src.size <> 16) | (@src.type = 'mem' and @src.size and not 8)
|
|
err 'invalid operand size'
|
|
end if
|
|
@src.memsize = 8
|
|
AVX_512.store_instruction@src 16,VEX_F3_0F_W0,EVEX_W1,7Eh,0,@dest.rm
|
|
else if @dest.type = 'mem' & @src.type = 'mmreg'
|
|
if @dest.size and not 8 | @src.size <> 16
|
|
err 'invalid operand size'
|
|
end if
|
|
@dest.memsize = 8
|
|
AVX_512.store_instruction@dest 16,VEX_66_0F_W0,EVEX_W1,0D6h,0,@src.rm
|
|
else if @dest.type = 'mmreg' & @src.type = 'reg'
|
|
if @dest.size <> 16 | @src.size <> 8
|
|
err 'invalid operand size'
|
|
end if
|
|
if x86.mode < 64
|
|
err 'instruction requires long mode'
|
|
end if
|
|
AVX_512.store_instruction@src 16,VEX_66_0F_W1,EVEX_W1,6Eh,0,@dest.rm
|
|
else if @dest.type = 'reg' & @src.type = 'mmreg'
|
|
if @dest.size <> 8 | @src.size <> 16
|
|
err 'invalid operand size'
|
|
end if
|
|
if x86.mode < 64
|
|
err 'instruction requires long mode'
|
|
end if
|
|
AVX_512.store_instruction@dest 16,VEX_66_0F_W1,EVEX_W1,7Eh,0,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
macro vmovddup? dest*,src*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem')
|
|
if @src.type = 'mem' & @dest.size = 16
|
|
if @src.size and not 8
|
|
err 'invalid operand size'
|
|
end if
|
|
@src.memsize = 8
|
|
else
|
|
if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
@src.memsize = @dest.size
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,VEX_F2_0F_W0,EVEX_W1+EVEX_VL,12h,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
iterate <instr,opcode>, vmovhlps,12h, vmovlhps,16h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_operand@src2 src2
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & @src2.type = 'mmreg'
|
|
if @dest.size <> 16
|
|
err 'invalid operand size'
|
|
else if @src.size <> @dest.size | @src2.size <> @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 16,VEX_0F_W0,EVEX_AS_VEX,opcode,0,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,evex_f,opcode>, vmovhpd,VEX_66_0F_W0,EVEX_W1,16h, vmovhps,VEX_0F_W0,EVEX_AS_VEX,16h, vmovlpd,VEX_66_0F_W0,EVEX_W1,12h, vmovlps,VEX_0F_W0,EVEX_AS_VEX,12h
|
|
|
|
macro instr? dest*,src*,src2
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
match , src2
|
|
if @dest.type = 'mem' & @src.type = 'mmreg'
|
|
if @dest.size and not 8 | @src.size <> 16
|
|
err 'invalid operand size'
|
|
end if
|
|
@dest.memsize = 8
|
|
AVX_512.store_instruction@dest 16,vex_mpw,evex_f,opcode+1,0,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
else
|
|
AVX_512.parse_operand@src2 src2
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & @src2.type = 'mem'
|
|
if @dest.size <> 16 | @src.size <> 16 | @src2.size and not 8
|
|
err 'invalid operand size'
|
|
end if
|
|
@src2.memsize = 8
|
|
AVX_512.store_instruction@src2 16,vex_mpw,evex_f,opcode,0,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end match
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,evex_f,opcode>, vmovntdq,VEX_66_0F_W0,EVEX_AS_VEX+EVEX_VL,0E7h, vmovntpd,VEX_66_0F_W0,EVEX_W1+EVEX_VL,2Bh, vmovntps,VEX_0F_W0,EVEX_AS_VEX+EVEX_VL,2Bh
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mem' & @src.type = 'mmreg'
|
|
if @dest.size and not @src.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@dest @src.size,vex_mpw,evex_f,opcode,0,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
macro vmovntdqa? dest*,src*
|
|
AVX_512.parse_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & @src.type = 'mem'
|
|
if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,2Ah,0,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
iterate <instr,vex_mpw,evex_f,msize>, vmovsd,VEX_F2_0F_W0,EVEX_W1,8, vmovss,VEX_F3_0F_W0,EVEX_AS_VEX,4
|
|
|
|
macro instr? dest*,src*,src2
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
match , src2
|
|
if @dest.type = 'mmreg' & @src.type = 'mem'
|
|
if @dest.size <> 16 | @src.size and not msize
|
|
err 'invalid operand size'
|
|
end if
|
|
@src.memsize = msize
|
|
AVX_512.store_instruction@src 16,vex_mpw,evex_f,10h,@dest.mask,@dest.rm
|
|
else if @dest.type = 'mem' & @src.type = 'mmreg'
|
|
if @dest.size and not msize | @src.size <> 16
|
|
err 'invalid operand size'
|
|
end if
|
|
@dest.memsize = msize
|
|
AVX_512.store_instruction@dest 16,vex_mpw,evex_f,11h,@dest.mask,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
else
|
|
AVX_512.parse_operand@src2 src2
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & @src2.type = 'mmreg'
|
|
if @dest.size <> 16 | @src.size <> 16 | @src2.size <> 16
|
|
err 'invalid operand size'
|
|
end if
|
|
AVX_512.store_instruction@src2 16,vex_mpw,evex_f,10h,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end match
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
macro vmovshdup? dest*,src*
|
|
AVX_512.single_source_instruction VEX_F3_0F_W0,EVEX_AS_VEX+EVEX_VL,16h,0,dest,src
|
|
end macro
|
|
|
|
macro vmovsldup? dest*,src*
|
|
AVX_512.single_source_instruction VEX_F3_0F_W0,EVEX_AS_VEX+EVEX_VL,12h,0,dest,src
|
|
end macro
|
|
|
|
iterate <instr,unit,evex_f,opcode_rrm,opcode_rri>, vpermilps,4,EVEX_AS_VEX+EVEX_VL,0Ch,4, vpermilpd,8,EVEX_W1+EVEX_VL,0Dh,5
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_bcst_operand@src src,unit
|
|
AVX_512.parse_bcst_operand@src2 src2,unit
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if @src.size <> @dest.size | @src2.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @dest.size,VEX_66_0F38_W0,evex_f,opcode_rrm,@dest.mask,@dest.rm,@src.rm
|
|
else if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @src2.type = 'imm'
|
|
if @src2.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F3A_W0,evex_f,opcode_rri,@dest.mask,@dest.rm,,1,@src2.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpaddd,0FEh, vpsubd,0FAh, vpunpckhdq,6Ah, vpunpckldq,62h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.basic_instruction_bcst VEX_66_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpaddq,0D4h, vpmuludq,0F4h, vpsubq,0FBh, vpunpckhqdq,6Dh, vpunpcklqdq,6Ch
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.basic_instruction_bcst VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpandd,0DBh, vpandnd,0DFh, vpord,0EBh, vpxord,0EFh
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.basic_instruction_bcst VEX_66_0F_W0,EVEX_REQUIRED+EVEX_VL,opcode,4,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpandq,0DBh, vpandnq,0DFh, vporq,0EBh, vpxorq,0EFh
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.basic_instruction_bcst VEX_66_0F_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpmaxsd,3Dh, vpmaxud,3Fh, vpminsd,39h, vpminud,3Bh, vpmulld,40h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.basic_instruction_bcst VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpmuldq,28h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.basic_instruction_bcst VEX_66_0F38_W0,EVEX_W1+EVEX_VL,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpmuldq,28h, vpmaxsq,3Dh, vpmaxuq,3Fh, vpminsq,39h, vpminuq,3Bh, vpmullq,40h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.basic_instruction_bcst VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpabsd,1Eh
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.single_source_instruction_bcst VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpabsq,1Fh
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.single_source_instruction_bcst VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw>, vpshufd,VEX_66_0F_W0
|
|
|
|
macro instr? dest*,src*,aux*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
x86.parse_operand@aux aux
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @aux.type = 'imm'
|
|
if @aux.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,EVEX_AS_VEX+EVEX_VL,70h,@dest.mask,@dest.rm,,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpsllvd,47h, vpsrlvd,45h, vpsravd,46h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.basic_instruction_bcst VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,opcode,4,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,evex_f,opcode>, vpsllvq,EVEX_AS_VEX+EVEX_VL,47h, vpsrlvq,EVEX_AS_VEX+EVEX_VL,45h, vpsravq,EVEX_REQUIRED+EVEX_VL,46h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.basic_instruction_bcst VEX_66_0F38_W1,evex_f,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,unit,vex_mpw,opcode>, vpermi2d,4,VEX_66_0F38_W0,76h, vpermi2q,8,VEX_66_0F38_W1,76h, \
|
|
vpermt2d,4,VEX_66_0F38_W0,7Eh, vpermt2q,8,VEX_66_0F38_W1,7Eh, \
|
|
vprorvd,4,VEX_66_0F38_W0,14h, vprorvq,8,VEX_66_0F38_W1,14h, \
|
|
vprolvd,4,VEX_66_0F38_W0,15h, vprolvq,8,VEX_66_0F38_W1,15h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.basic_instruction_bcst vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,unit,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,unit,vex_mpw,postbyte>, vprord,4,VEX_66_0F_W0,0, vprorq,8,VEX_66_0F_W1,0, vprold,4,VEX_66_0F_W0,1, vprolq,8,VEX_66_0F_W1,1
|
|
|
|
macro instr? dest*,src*,aux*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_bcst_operand@src src,unit
|
|
x86.parse_operand@aux aux
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @aux.type = 'imm'
|
|
if @src.size and not @dest.size | @aux.size and not 1
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,72h,@dest.mask,postbyte,@dest.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode_rrm,opcode,postbyte>, vpslld,0F2h,72h,6, vpsrad,0E2h,72h,4, vpsrld,0D2h,72h,2
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src2 src2
|
|
if @src2.type = 'imm'
|
|
AVX_512.parse_bcst_operand@src src,4
|
|
else
|
|
AVX_512.parse_operand@src src
|
|
end if
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
@src2.memsize = 16
|
|
if @src2.size and not @src2.memsize
|
|
err 'invalid operand size'
|
|
else if @src.size <> @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @dest.size,VEX_66_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode_rrm,@dest.mask,@dest.rm,@src.rm
|
|
else if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem') & @src2.type = 'imm'
|
|
if @src2.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src.size <> @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
if @src.type = 'mem'
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F_W0,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,postbyte,@dest.rm,1,@src2.imm
|
|
else
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F_W0,EVEX_AS_VEX+EVEX_VL,opcode,@dest.mask,postbyte,@dest.rm,1,@src2.imm
|
|
end if
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode_rrm,opcode,postbyte>, vpsllq,0F3h,73h,6, vpsraq,0E2h,72h,4, vpsrlq,0D3h,73h,2
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src2 src2
|
|
if @src2.type = 'imm'
|
|
AVX_512.parse_bcst_operand@src src,8
|
|
else
|
|
AVX_512.parse_operand@src src
|
|
end if
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
@src2.memsize = 16
|
|
if @src2.size and not @src2.memsize
|
|
err 'invalid operand size'
|
|
else if @src.size <> @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
if `instr = 'vpsraq'
|
|
AVX_512.store_instruction@src2 @dest.size,VEX_66_0F_W1,EVEX_REQUIRED+EVEX_VL,opcode_rrm,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
AVX_512.store_instruction@src2 @dest.size,VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode_rrm,@dest.mask,@dest.rm,@src.rm
|
|
end if
|
|
else if @dest.type = 'mmreg' & (@src.type = 'mmreg' | @src.type = 'mem') & @src2.type = 'imm'
|
|
if @src2.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
if @src.type = 'mem' | `instr = 'vpsraq'
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F_W1,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,postbyte,@dest.rm,1,@src2.imm
|
|
else
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F_W0,EVEX_W1+EVEX_VL,opcode,@dest.mask,postbyte,@dest.rm,1,@src2.imm
|
|
end if
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpcmpeqd,76h, vpcmpgtd,66h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.parse_k1_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_bcst_operand@src2 src2,4
|
|
if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if @src2.size and not @src.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @src.size,VEX_66_0F_W0,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if @src.size <> @dest.size | @src2.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @src.size,VEX_66_0F_W0,EVEX_FORBIDDEN,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpcmpeqq,29h, vpcmpgtq,37h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.parse_k1_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_bcst_operand@src2 src2,8
|
|
if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if @src2.size and not @src.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @src.size,VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if @src.size <> @dest.size | @src2.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @src.size,VEX_66_0F38_W0,EVEX_FORBIDDEN,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,unit,vex_mpw,opcode>, vptestnmd,4,VEX_F3_0F38_W0,27h, vptestnmq,8,VEX_F3_0F38_W1,27h, vptestmd,4,VEX_66_0F38_W0,27h, vptestmq,8,VEX_66_0F38_W1,27h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.parse_k1_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_bcst_operand@src2 src2,unit
|
|
if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if @src2.size and not @src.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,unit,vex_mpw,opcode>, vpcmpd,4,VEX_66_0F3A_W0,1Fh, vpcmpud,4,VEX_66_0F3A_W0,1Eh, vpcmpq,8,VEX_66_0F3A_W1,1Fh, vpcmpuq,8,VEX_66_0F3A_W1,1Eh
|
|
|
|
macro instr? dest*,src*,src2*,aux*
|
|
AVX_512.parse_k1_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_bcst_operand@src2 src2,unit
|
|
x86.parse_operand@aux aux
|
|
if @dest.type = 'maskreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg') & @aux.type = 'imm'
|
|
if @src2.size and not @src.size | @aux.size and not 1
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@dest.rm,@src.rm,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode,msize>, vpmovsxbd,21h,4, vpmovsxbq,22h,2, vpmovsxwd,23h,8, vpmovsxwq,24h,4, vpmovsxdq,25h,8, \
|
|
vpmovzxbd,31h,4, vpmovzxbq,32h,2, vpmovzxwd,33h,8, vpmovzxwq,34h,4, vpmovzxdq,35h,8
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg')
|
|
@src.memsize = msize * (@dest.size shr 4)
|
|
if (@src.type = 'mmreg' & @src.size <> (@src.memsize-1) and not 15 + 16) | (@src.type = 'mem' & @src.size and not @src.memsize)
|
|
err 'invalid operand size'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,opcode,@dest.mask,@dest.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpermq,0, vpermpd,1
|
|
|
|
macro instr? dest*,src*,aux*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_bcst_operand@src src,8
|
|
x86.parse_operand@aux aux
|
|
if @dest.type = 'mmreg' & (@src.type = 'mem' | @src.type = 'mmreg') & @aux.type = 'imm'
|
|
if @dest.size < 32 | @aux.size and not 1
|
|
err 'invalid operand size'
|
|
else if @src.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F3A_W1,EVEX_AS_VEX+EVEX_VL,opcode,@dest.mask,@dest.rm,,1,@aux.imm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vpermd,36h, vpermps,16h
|
|
|
|
macro instr? dest*,src*,src2*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
AVX_512.parse_bcst_operand@src2 src2,4
|
|
if @dest.type = 'mmreg' & @src.type = 'mmreg' & (@src2.type = 'mem' | @src2.type = 'mmreg')
|
|
if @dest.size < 32
|
|
err 'invalid operand size'
|
|
else if @src.size <> @dest.size | @src2.size and not @dest.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@src2 @dest.size,VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,opcode,@dest.mask,@dest.rm,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,lcode>, vfmaddsub,6, vfmsubadd,7, vfmaddsub,8, vfmsub,0Ah, vfnmadd,0Ch, vfnmsub,0Eh
|
|
|
|
iterate <order,hcode>, 132,90h, 213,0A0h, 231,0B0h
|
|
|
|
macro instr#order#pd? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst_er VEX_66_0F38_W1,EVEX_AS_VEX+EVEX_VL,hcode+lcode,8,dest,src,src2
|
|
end macro
|
|
|
|
macro instr#order#ps? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst_er VEX_66_0F38_W0,EVEX_AS_VEX+EVEX_VL,hcode+lcode,4,dest,src,src2
|
|
end macro
|
|
|
|
if lcode > 7
|
|
|
|
macro instr#order#sd? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_er VEX_66_0F38_W1,EVEX_AS_VEX,hcode+lcode+1,8,dest,src,src2
|
|
end macro
|
|
|
|
macro instr#order#ss? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_er VEX_66_0F38_W0,EVEX_AS_VEX,hcode+lcode+1,4,dest,src,src2
|
|
end macro
|
|
|
|
end if
|
|
|
|
end iterate
|
|
|
|
end iterate
|
|
|
|
iterate <instr,unit,vex_mpw,opcode>, valignd,4,VEX_66_0F3A_W0,3, vpternlogd,4,VEX_66_0F3A_W0,25h, vpternlogq,8,VEX_66_0F3A_W1,25h
|
|
|
|
macro instr? dest*,src*,src2*,aux*&
|
|
AVX_512.basic_instruction_bcst_imm8 vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,unit,dest,src,src2,aux
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, valignq,3
|
|
|
|
macro instr? dest*,src*,src2*,aux*&
|
|
AVX_512.basic_instruction_bcst_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2,aux
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vblendmps,65h, vpblendmd,64h
|
|
|
|
macro instr? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,4,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, vblendmpd,65h, vpblendmq,64h
|
|
|
|
macro instr? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,unit,vex_mpw,opcode>, vrcp14ps,4,VEX_66_0F38_W0,4Ch, vrcp14pd,8,VEX_66_0F38_W1,4Ch, vrsqrt14ps,4,VEX_66_0F38_W0,4Eh, vrsqrt14pd,8,VEX_66_0F38_W1,4Eh
|
|
|
|
macro instr? dest*,src*&
|
|
AVX_512.single_source_instruction_bcst vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,unit,dest,src
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,unit,vex_mpw,opcode>, vrcp14ss,4,VEX_66_0F38_W0,4Dh, vrcp14sd,8,VEX_66_0F38_W1,4Dh, vrsqrt14ss,4,VEX_66_0F38_W0,4Fh, vrsqrt14sd,8,VEX_66_0F38_W1,4Fh
|
|
|
|
macro instr? dest*,src*&
|
|
AVX_512.basic_instruction vex_mpw,EVEX_REQUIRED,opcode,unit,dest,src
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,opcode>, vcompressps,VEX_66_0F_W0,8Ah, vcompresspd,VEX_66_0F_W1,8Ah, vpcompressd,VEX_66_0F38_W0,8Bh, vpcompressq,VEX_66_0F38_W1,8Bh
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.parse_k1z_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if (@dest.type = 'mmreg' | @dest.type = 'mem') & @src.type = 'mmreg'
|
|
if @dest.size and not @src.size
|
|
err 'operand sizes do not match'
|
|
end if
|
|
AVX_512.store_instruction@dest @src.size,vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@src.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,vex_mpw,opcode>, vexpandps,VEX_66_0F38_W0,88h, vexpandpd,VEX_66_0F38_W1,88h, vpexpandd,VEX_66_0F38_W0,89h, vpexpandq,VEX_66_0F38_W1,89h
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.single_source_instruction vex_mpw,EVEX_REQUIRED+EVEX_VL,opcode,0,dest,src
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, fixupimm,54h
|
|
|
|
macro v#instr#pd? dest*,src*,src2*,aux*&
|
|
AVX_512.basic_instruction_bcst_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src,src2,aux
|
|
end macro
|
|
|
|
macro v#instr#ps? dest*,src*,src2*,aux*&
|
|
AVX_512.basic_instruction_bcst_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED+EVEX_VL,opcode,4,dest,src,src2,aux
|
|
end macro
|
|
|
|
macro v#instr#sd? dest*,src*,src2*,aux*&
|
|
AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED,opcode+1,8,dest,src,src2,aux
|
|
end macro
|
|
|
|
macro v#instr#ss? dest*,src*,src2*,aux*&
|
|
AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED,opcode+1,4,dest,src,src2,aux
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode>, getexp,42h
|
|
|
|
macro v#instr#pd? dest*,src*&
|
|
AVX_512.single_source_instruction_bcst_sae VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,8,dest,src
|
|
end macro
|
|
|
|
macro v#instr#ps? dest*,src*&
|
|
AVX_512.single_source_instruction_bcst_sae VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,4,dest,src
|
|
end macro
|
|
|
|
macro v#instr#sd? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_sae VEX_66_0F38_W1,EVEX_REQUIRED,opcode+1,8,dest,src,src2
|
|
end macro
|
|
|
|
macro v#instr#ss? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_sae VEX_66_0F38_W0,EVEX_REQUIRED,opcode+1,4,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode_ps,opcode_pd,opcode_ss,opcode_sd>, getmant,26h,26h,27h,27h, rndscale,8,9,0Ah,0Bh
|
|
|
|
macro v#instr#pd? dest*,src*,aux*&
|
|
AVX_512.single_source_instruction_bcst_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED+EVEX_VL,opcode_pd,8,dest,src,aux
|
|
end macro
|
|
|
|
macro v#instr#ps? dest*,src*,aux*&
|
|
AVX_512.single_source_instruction_bcst_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED+EVEX_VL,opcode_ps,4,dest,src,aux
|
|
end macro
|
|
|
|
macro v#instr#sd? dest*,src*,src2*,aux*&
|
|
AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W1,EVEX_REQUIRED,opcode_sd,8,dest,src,src2,aux
|
|
end macro
|
|
|
|
macro v#instr#ss? dest*,src*,src2*,aux*&
|
|
AVX_512.basic_instruction_sae_imm8 VEX_66_0F3A_W0,EVEX_REQUIRED,opcode_ss,4,dest,src,src2,aux
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,unit,vex_mpw>, vscalefpd,8,VEX_66_0F38_W1, vscalefps,4,VEX_66_0F38_W0
|
|
|
|
macro instr? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_bcst_er vex_mpw,EVEX_REQUIRED+EVEX_VL,2Ch,unit,dest,src,src2
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,unit,vex_mpw>, vscalefsd,8,VEX_66_0F38_W1, vscalefss,4,VEX_66_0F38_W0
|
|
|
|
macro instr? dest*,src*,src2*&
|
|
AVX_512.basic_instruction_er vex_mpw,EVEX_REQUIRED,2Dh,unit,dest,src,src2
|
|
end macro
|
|
|
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end iterate
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iterate <instr,ratio,opcode>, vpmovusdb,4,11h, vpmovsdb,4,21h, vpmovdb,4,31h, \
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vpmovusqb,8,12h, vpmovsqb,8,22h, vpmovqb,8,32h, \
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vpmovusdw,2,13h, vpmovsdw,2,23h, vpmovdw,2,33h, \
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vpmovusqw,4,14h, vpmovsqw,4,24h, vpmovqw,4,34h, \
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vpmovusqd,2,15h, vpmovsqd,2,25h, vpmovqd,2,35h
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macro instr? dest*,src*
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AVX_512.parse_k1z_operand@dest dest
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AVX_512.parse_operand@src src
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if (@dest.type = 'mmreg' | @dest.type = 'mem') & @src.type = 'mmreg'
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@dest.memsize = @src.size / ratio
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if (@dest.type = 'mmreg' & @dest.size <> (@dest.memsize-1) and not 15 + 16) | (@dest.type = 'mem' & @dest.size and not @dest.memsize)
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err 'invalid operand size'
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end if
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AVX_512.store_instruction@dest @src.size,VEX_F3_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@src.rm
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else
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err 'invalid combination of operands'
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end if
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end macro
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|
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end iterate
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iterate <instr,opcode,asize>, vpgatherdd,90h,4, vpgatherqd,91h,8, vgatherdps,92h,4, vgatherqps,93h,8
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macro instr? dest*,src*,aux
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match , aux
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AVX_512.parse_k1_operand@dest dest
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AVX_512.parse_vsib_operand@src src
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if @dest.type = 'mmreg' & @dest.mask & @src.type = 'mem'
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if @src.size and not 4 | (@dest.size > 16 & @dest.size * (asize shr 2) > @src.visize) | (@src.visize > 16 & @dest.size * (asize shr 2) < @src.visize)
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err 'invalid operand size'
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else if @dest.rm = @src.index
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|
err 'disallowed combination of registers'
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|
end if
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@src.memsize = 4
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AVX_512.store_instruction@src @src.visize,VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@dest.rm,@src.index and 10000b
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else
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err 'invalid combination of operands'
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|
end if
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|
else
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|
AVX.parse_operand@dest dest
|
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AVX.parse_vsib_operand@src src
|
|
AVX.parse_operand@aux aux
|
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if @dest.type = 'mmreg' & @src.type = 'mem' & @aux.type = 'mmreg'
|
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if @src.size and not 4 | (@dest.size > 16 & @dest.size * (asize shr 2) > @src.visize) | (@src.visize > 16 & @dest.size * (asize shr 2) < @src.visize)
|
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err 'invalid operand size'
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|
else if @aux.size <> @dest.size
|
|
err 'operand sizes do not match'
|
|
else if @dest.rm = @aux.rm | @dest.rm = @src.index | @aux.rm = @src.index
|
|
err 'disallowed combination of registers'
|
|
end if
|
|
AVX.store_instruction@src @src.visize,VEX_66_0F38_W0,opcode,@dest.rm,@aux.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end match
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode,asize>, vpgatherdq,90h,4, vpgatherqq,91h,8, vgatherdpd,92h,4, vgatherqpd,93h,8
|
|
|
|
macro instr? dest*,src*,aux
|
|
match , aux
|
|
AVX_512.parse_k1_operand@dest dest
|
|
AVX_512.parse_vsib_operand@src src
|
|
if @dest.type = 'mmreg' & @dest.mask & @src.type = 'mem'
|
|
if @src.size and not 8 | (@dest.size > 16 & @dest.size * (asize shr 2) > @src.visize * 2) | (@src.visize > 16 & @dest.size * (asize shr 2) < @src.visize * 2)
|
|
err 'invalid operand size'
|
|
else if @dest.rm = @src.index
|
|
err 'disallowed combination of registers'
|
|
end if
|
|
@src.memsize = 8
|
|
AVX_512.store_instruction@src @dest.size,VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@dest.rm,@src.index and 10000b
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
else
|
|
AVX.parse_operand@dest dest
|
|
AVX.parse_vsib_operand@src src
|
|
AVX.parse_operand@aux aux
|
|
if @dest.type = 'mmreg' & @src.type = 'mem' & @aux.type = 'mmreg'
|
|
if @src.size and not 8 | (@dest.size > 16 & @dest.size * (asize shr 2) > @src.visize * 2) | (@src.visize > 16 & @dest.size * (asize shr 2) < @src.visize * 2)
|
|
err 'invalid operand size'
|
|
else if @aux.size <> @dest.size
|
|
err 'operand sizes do not match'
|
|
else if @dest.rm = @aux.rm | @dest.rm = @src.index | @aux.rm = @src.index
|
|
err 'disallowed combination of registers'
|
|
end if
|
|
AVX.store_instruction@src @dest.size,VEX_66_0F38_W1,opcode,@dest.rm,@aux.rm
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end match
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode,asize>, vpscatterdd,0A0h,4, vpscatterqd,0A1h,8, vscatterdps,0A2h,4, vscatterqps,0A3h,8
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.parse_k1_vsib_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mem' & @dest.mask & @src.type = 'mmreg'
|
|
if @dest.size and not 4 | (@src.size > 16 & @src.size * (asize shr 2) > @dest.visize) | (@dest.visize > 16 & @src.size * (asize shr 2) < @dest.visize)
|
|
err 'invalid operand size'
|
|
else if @src.rm = @dest.index
|
|
err 'disallowed combination of registers'
|
|
end if
|
|
@dest.memsize = 4
|
|
AVX_512.store_instruction@dest @dest.visize,VEX_66_0F38_W0,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@src.rm,@dest.index and 10000b
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
iterate <instr,opcode,asize>, vpscatterdq,0A0h,4, vpscatterqq,0A1h,8, vscatterdpd,0A2h,4, vscatterqpd,0A3h,8
|
|
|
|
macro instr? dest*,src*
|
|
AVX_512.parse_k1_vsib_operand@dest dest
|
|
AVX_512.parse_operand@src src
|
|
if @dest.type = 'mem' & @dest.mask & @src.type = 'mmreg'
|
|
if @dest.size and not 8 | (@src.size > 16 & @src.size * (asize shr 2) > @dest.visize * 2) | (@dest.visize > 16 & @src.size * (asize shr 2) < @dest.visize * 2)
|
|
err 'invalid operand size'
|
|
else if @src.rm = @dest.index
|
|
err 'disallowed combination of registers'
|
|
end if
|
|
@dest.memsize = 8
|
|
AVX_512.store_instruction@dest @src.size,VEX_66_0F38_W1,EVEX_REQUIRED+EVEX_VL,opcode,@dest.mask,@src.rm,@dest.index and 10000b
|
|
else
|
|
err 'invalid combination of operands'
|
|
end if
|
|
end macro
|
|
|
|
end iterate
|
|
|
|
end if
|