add flat assembler toolchain
This commit is contained in:
903
toolchain/fasmg.kl0e/examples/avr/avr.inc
Normal file
903
toolchain/fasmg.kl0e/examples/avr/avr.inc
Normal file
@ -0,0 +1,903 @@
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element R
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repeat 32 i:0
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element R#i? : R + i
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end repeat
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XH? = R27
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XL? = R26
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YH? = R29
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YL? = R28
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ZH? = R31
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ZL? = R30
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element X
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element Y
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element Z
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iterate <instr,opcode>, ADC,000111b, ADD,000011b, AND, 001000b, EOR, 001001b, CP,000101b, CPC,000001b, CPSE,000100b, MOV,001011b, MUL,100111b, OR,001010b, SBC,000010b, SUB,000110b
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macro instr? Rd,Rr
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local value,d,r
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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value = +Rr
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if value metadata 1 relativeto R & value eq value element 1
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r = value metadata 1 - R
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dw r and 1111b + d shl 4 + (r shr 4) shl 9 + opcode shl 10
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else
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err 'invalid operand'
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end if
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else
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err 'invalid operand'
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end if
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end macro
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end iterate
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iterate <instr,opcode>, ADIW,10010110b, SBIW,10010111b
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macro instr? RRd,K
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local value,d
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match Rdh:Rdl,RRd
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value = +Rdl
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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value = +Rdh
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if value metadata 1 relativeto R & value eq value element 1
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if value metadata 1 - R = d + 1
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if d = 24 | d = 26 | d = 28 | d = 30
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value = +K
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if value >= 0 & value <= 63
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dw value and 1111b + ((d-24) shr 1) shl 4 + (value shr 4) shl 6 + opcode shl 8
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else
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err 'immediate value out of range'
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end if
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else
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err 'specified register not allowed for this instruction'
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end if
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else
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err 'invalid operand'
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end if
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else
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err 'invalid operand'
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end if
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else
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err 'invalid operand'
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end if
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else match Rd,RRd
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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if d = 24 | d = 26 | d = 28 | d = 30
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value = +K
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if value >= 0 & value <= 63
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dw value and 1111b + ((d-24) shr 1) shl 4 + (value shr 4) shl 6 + opcode shl 8
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else
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err 'immediate value out of range'
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end if
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else
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err 'specified register not allowed for this instruction'
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end if
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else
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err 'invalid operand'
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end if
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else
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err 'invalid operand'
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end match
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end macro
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end iterate
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iterate <instr,opcode>, ANDI,0111b, CPI,0011b, LDI,1110b, ORI,0110b, SBCI,0100b, SBR,0110b, SUBI,0101b
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macro instr? Rd,K
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local value,d
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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if d >= 16
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value = +K
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if value >= -256 & value <= 255
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value = value and 0FFh
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dw value and 1111b + (d-16) shl 4 + (value shr 4) shl 8 + opcode shl 12
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else
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err 'immediate value out of range'
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end if
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else
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err 'specified register not allowed for this instruction'
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end if
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else
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err 'invalid operand'
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end if
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end macro
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end iterate
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iterate <instr,opcode>, ASR,0101b, COM,0000b, DEC,1010b, INC,0011b, LSR,0110b, NEG,0001b, ROR,0111b, SWAP,0010b
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macro instr? Rd
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local value,d
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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dw opcode + d shl 4 + 1001010b shl 9
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else
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err 'invalid operand'
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end if
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end macro
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end iterate
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iterate <instr,opcode>, BCLR,1001'0100'1000'1000b, BSET,1001'0100'0000'1000b
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macro instr? s
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local value
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value = +s
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if value >= 0 & value <= 7
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dw opcode + value shl 4
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else
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err 'bit index out of range'
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end if
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end macro
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end iterate
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iterate <instr,opcode>, BLD,1111100b, BST,1111101b, SBRC,1111110b, SBRS,1111111b
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macro instr? Rd,b
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local value,d
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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value = +b
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if value >= 0 & value <= 7
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dw value + d shl 4 + opcode shl 9
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else
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err 'bit index out of range'
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end if
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else
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err 'invalid operand'
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end if
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end macro
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end iterate
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iterate <instr,opcode>, BRBC,111101b, BRBS,111100b
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macro instr? s,k
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local index,offset
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index = +s
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if index >= 0 & index <= 7
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offset = -($ shr 1 + 1) + k
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if offset >= -64 & offset <= 63
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dw index + (offset and 1111111b) shl 3 + opcode shl 10
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else
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err 'relative jump out of range'
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end if
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else
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err 'bit index out of range'
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end if
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end macro
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end iterate
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macro BRCC? k
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BRBC 0,k
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end macro
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macro BRCS? k
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BRBS 0,k
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end macro
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macro BREQ? k
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BRBS 1,k
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end macro
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macro BRGE? k
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BRBC 4,k
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end macro
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macro BRHC? k
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BRBC 5,k
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end macro
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macro BRHS? k
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BRBS 5,k
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end macro
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macro BRID? k
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BRBC 7,k
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end macro
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macro BRIE? k
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BRBS 7,k
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end macro
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macro BRLO? k
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BRBS 0,k
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end macro
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macro BRLT? k
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BRBS 4,k
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end macro
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macro BRMI? k
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BRBS 2,k
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end macro
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macro BRNE? k
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BRBC 1,k
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end macro
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macro BRPL? k
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BRBC 2,k
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end macro
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macro BRSH? k
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BRBC 0,k
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end macro
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macro BRTC? k
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BRBC 6,k
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end macro
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macro BRTS? k
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BRBS 6,k
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end macro
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macro BRVC? k
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BRBC 3,k
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end macro
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macro BRVS? k
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BRBS 3,k
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end macro
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macro CALL? k
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local offset
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offset = -($ shr 1 + 1) + k
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if offset >= -2048 & offset <= 2047
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dw offset and (1 shl 12 - 1) + 1101b shl 12
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else
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offset = +k
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if offset >= 0 & offset <= 1 shl 22 - 1
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dw (offset shr 16) and 1 + 111b shl 1 + (offset shr 17) shl 4 + 1001010b shl 9
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dw offset and (1 shl 16 - 1)
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else
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err 'value out of range'
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end if
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end if
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end macro
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iterate <instr,opcode>, CBI,10011000b, SBI,10011010b, SBIC,10011001b, SBIS,10011011b
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macro instr? A,b
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local reg,index
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reg = +A
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if reg >= 0 & reg <= 31
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index = +b
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if index >= 0 & index <= 7
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dw index + reg shl 3 + opcode shl 8
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else
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err 'bit index out of range'
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end if
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else
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err 'specified register number not allowed'
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end if
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end macro
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end iterate
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macro CBR? r,K
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ANDI r,$FF-(K)
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end macro
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macro CLC?
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dw 1001'0100'1000'1000b
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end macro
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macro CLH?
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dw 1001'0100'1101'1000b
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end macro
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macro CLI?
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dw 1001'0100'1111'1000b
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end macro
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macro CLN?
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dw 1001'0100'1010'1000b
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end macro
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macro CLR? r
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EOR r,r
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end macro
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macro CLS?
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dw 1001'0100'1100'1000b
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end macro
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macro CLT?
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dw 1001'0100'1110'1000b
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end macro
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macro CLV?
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dw 1001'0100'1011'1000b
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end macro
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macro CLZ?
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dw 1001'0100'1001'1000b
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end macro
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macro DES? K
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local value
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value = +K
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if value >= 0 & value <= 0x0F
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dw 1011b + value shl 4 + 10010100b shl 8
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else
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err 'value out of range'
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end if
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end macro
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macro EICALL?
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dw 1001'0101'0001'1001b
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end macro
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macro EIJMP?
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dw 1001'0100'0001'1001b
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end macro
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iterate <instr,opcode,opcode2,opcode3>, ELPM,1001'0101'1101'1000b,0110b,0111b, LPM,1001'0101'1100'1000b,0100b,0101b
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macro instr? args&
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local value,d
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match , args
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dw opcode
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else match Rd=, =Z?, args
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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dw opcode2 + d shl 4 + 1001000b shl 9
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else
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err 'invalid operand'
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end if
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else match Rd=, =Z?+, args
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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dw opcode3 + d shl 4 + 1001000b shl 9
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else
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err 'invalid operand'
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end if
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else
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err 'invalid operand'
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end match
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end macro
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end iterate
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iterate <instr,opcode>, FMUL,1100001000b, FMULS,1110000000b, FMULSU,1110001000b
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macro instr? Rd,Rr
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local value,d,r
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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if d >= 16 & d <= 23
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value = +Rr
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if value metadata 1 relativeto R & value eq value element 1
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r = value metadata 1 - R
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if r >= 16 & r <= 23
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dw opcode + (r-16) + (d-16) shl 4
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else
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err 'specified register not allowed for this instruction'
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end if
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else
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err 'invalid operand'
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end if
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else
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err 'specified register not allowed for this instruction'
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end if
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else
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err 'invalid operand'
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end if
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end macro
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end iterate
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macro ICALL?
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dw 1001'0101'0000'1001b
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end macro
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macro IJMP?
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dw 1001'0100'0000'1001b
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end macro
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macro IN? Rd,A
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local value,d
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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value = +A
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if A >= 0 & A <= 63
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dw A and 1111b + d shl 4 + (A shr 4) shl 9 + 10110b shl 11
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else
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err 'address out of range'
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end if
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else
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err 'invalid operand'
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end if
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end macro
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macro JMP? k
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local offset
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offset = -($ shr 1 + 1) + k
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if offset>=-2048 & offset<=2047
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dw offset and 111111111111b + 1100b shl 12
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else
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offset = +k
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if offset>=0 & offset<=1 shl 22 - 1
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dw (offset shr 16) and 1 + 110b shl 1 + (offset shr 17) shl 4 + 1001010b shl 9
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dw offset and (1 shl 16 - 1)
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else
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err 'value out of range'
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end if
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end if
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end macro
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iterate <instr,opcode>, LAC,0110b, LAS,0101b, LAT,0111b, XCH,0100b
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macro instr? Rw,Rd
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local value,d
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match =Z?, Rw
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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dw opcode + d shl 4 + 1001001b shl 9
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else
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err 'invalid operand'
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end if
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else
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err 'invalid operand'
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end match
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end macro
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end iterate
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macro LD? Rd,Rw
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local value,d
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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match =X?, Rw
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dw 1100b + d shl 4 + 1001000b shl 9
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else match =Y?, Rw
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dw 1000b + d shl 4 + 1000000b shl 9
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else match =Z?, Rw
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dw 0000b + d shl 4 + 1000000b shl 9
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else match =X?+, Rw
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dw 1101b + d shl 4 + 1001000b shl 9
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else match =Y?+, Rw
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dw 1001b + d shl 4 + 1001000b shl 9
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else match =Z?+, Rw
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dw 0001b + d shl 4 + 1001000b shl 9
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else match -=X?, Rw
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dw 1110b + d shl 4 + 1001000b shl 9
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else match -=Y?, Rw
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dw 1010b + d shl 4 + 1001000b shl 9
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else match -=Z?, Rw
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dw 0010b + d shl 4 + 1001000b shl 9
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else
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err 'invalid operand'
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end match
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else
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err 'invalid operand'
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end if
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end macro
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macro LDD? Rd,Rq
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local value,d,q
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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value = +Rq
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if value relativeto Y
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q = value - Y
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if q >= 0 & q <= 63
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dw q and 111b + 1 shl 3 + d shl 4 + ((q shr 3) and 11b) shl 10 + (q shr 5) shl 13 + 10b shl 14
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else
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err 'value out of range'
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end if
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else if value relativeto Z
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q = value - Z
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if q >= 0 & q <= 63
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dw q and 111b + d shl 4 + ((q shr 3) and 11b) shl 10 + (q shr 5) shl 13 + 10b shl 14
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else
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err 'value out of range'
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end if
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||||
else
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err 'invalid operand'
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||||
end if
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||||
else
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err 'invalid operand'
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||||
end if
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||||
end macro
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macro LDS? Rd,k
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local value,d
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value = +Rd
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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value = +k
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if value >= 0 & value <= 65535
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dw d shl 4 + 1001000b shl 9
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dw value
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else
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err 'address out of range'
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end if
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else
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err 'invalid operand'
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end if
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end macro
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macro LSL? r
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ADD r,r
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end macro
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macro MOVW? args&
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local value,d,r
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match Rdh:Rdl=,Rrh:Rrl, args
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value = +Rdl
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if value metadata 1 relativeto R & value eq value element 1
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d = value metadata 1 - R
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value = +Rdh
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if value metadata 1 relativeto R & value eq value element 1
|
||||
if value metadata 1 - R = d + 1 & d and 1 = 0
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value = +Rrl
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if value metadata 1 relativeto R & value eq value element 1
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r = value metadata 1 - R
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||||
value = +Rrh
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||||
if value metadata 1 relativeto R & value eq value element 1
|
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if value metadata 1 - R = r + 1 & r and 1 = 0
|
||||
dw r shr 1 + (d shr 1) shl 4 + 1 shl 8
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else match Rd=,Rr,args
|
||||
value = +Rd
|
||||
if value metadata 1 relativeto R & value eq value element 1
|
||||
d = value metadata 1 - R
|
||||
if d and 1 = 0
|
||||
value = +Rr
|
||||
if value metadata 1 relativeto R & value eq value element 1
|
||||
r = value metadata 1 - R
|
||||
if r and 1 = 0
|
||||
dw r shr 1 + (d shr 1) shl 4 + 1 shl 8
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end match
|
||||
end macro
|
||||
|
||||
iterate <instr,opcode>, MULS,0010b, MULSU,0011b
|
||||
macro instr? Rd,Rr
|
||||
local value,d,r
|
||||
value = +Rd
|
||||
if value metadata 1 relativeto R & value eq value element 1
|
||||
d = value metadata 1 - R
|
||||
if d >= 16 & d <= 31
|
||||
value = +Rr
|
||||
if value metadata 1 relativeto R & value eq value element 1
|
||||
r = value metadata 1 - R
|
||||
if r >= 16 & r <= 31
|
||||
dw (r-16) + (d-16) shl 4 + opcode shl 8
|
||||
else
|
||||
err 'specified register not allowed for this instruction'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'specified register not allowed for this instruction'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
end macro
|
||||
end iterate
|
||||
|
||||
macro NOP?
|
||||
dw 0
|
||||
end macro
|
||||
|
||||
macro OUT? A,Rr
|
||||
local value,r
|
||||
value = +Rr
|
||||
if value metadata 1 relativeto R & value eq value element 1
|
||||
r = value metadata 1 - R
|
||||
value = +A
|
||||
if A >= 0 & A <= 63
|
||||
dw A and 1111b + r shl 4 + (A shr 4) shl 9 + 10111b shl 11
|
||||
else
|
||||
err 'address out of range'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
end macro
|
||||
|
||||
iterate <instr,opcode>, POP,000b, PUSH,001b
|
||||
macro instr? Rd
|
||||
local value,d
|
||||
value = +Rd
|
||||
if value metadata 1 relativeto R & value eq value element 1
|
||||
d = value metadata 1 - R
|
||||
dw 1111b + d shl 4 + opcode shl 9 + 1001b shl 12
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
end macro
|
||||
end iterate
|
||||
|
||||
iterate <instr,opcode>, RCALL,1101b, RJMP,1100b
|
||||
macro instr? k
|
||||
local offset
|
||||
offset = -($ shr 1 + 1) + k
|
||||
if offset>=-2048 & offset<=2047
|
||||
dw offset and 111111111111b + opcode shl 12
|
||||
else
|
||||
err 'relative jump out of range'
|
||||
end if
|
||||
end macro
|
||||
end iterate
|
||||
|
||||
macro RET?
|
||||
dw 1001'0101'0000'1000b
|
||||
end macro
|
||||
|
||||
macro RETI?
|
||||
dw 1001'0101'0001'1000b
|
||||
end macro
|
||||
|
||||
macro ROL? r
|
||||
ADC r,r
|
||||
end macro
|
||||
|
||||
macro SEC?
|
||||
dw 1001'0100'0000'1000b
|
||||
end macro
|
||||
|
||||
macro SEH?
|
||||
dw 1001'0100'0101'1000b
|
||||
end macro
|
||||
|
||||
macro SEI?
|
||||
dw 1001'0100'0111'1000b
|
||||
end macro
|
||||
|
||||
macro SEN?
|
||||
dw 1001'0100'0010'1000b
|
||||
end macro
|
||||
|
||||
macro SER? Rd
|
||||
local value,d
|
||||
value = +Rd
|
||||
if value metadata 1 relativeto R & value eq value element 1
|
||||
d = value metadata 1 - R
|
||||
if d >= 16
|
||||
dw 1111b + (d-16) shl 4 + 11101111b shl 8
|
||||
else
|
||||
err 'specified register not allowed for this instruction'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
end macro
|
||||
|
||||
macro SES?
|
||||
dw 1001'0100'0100'1000b
|
||||
end macro
|
||||
|
||||
macro SET?
|
||||
dw 1001'0100'0110'1000b
|
||||
end macro
|
||||
|
||||
macro SEV?
|
||||
dw 1001'0100'0011'1000b
|
||||
end macro
|
||||
|
||||
macro SEZ?
|
||||
dw 1001'0100'0001'1000b
|
||||
end macro
|
||||
|
||||
macro SLEEP?
|
||||
dw 1001'0101'1000'1000b
|
||||
end macro
|
||||
|
||||
macro SPM? args
|
||||
match , args
|
||||
dw 1001'0101'1110'1000b
|
||||
else match =Z?+,args
|
||||
dw 1001'0101'1111'1000b
|
||||
else
|
||||
err 'invalid operand'
|
||||
end match
|
||||
end macro
|
||||
|
||||
macro ST? Rw,Rr
|
||||
local value,r
|
||||
value = +Rr
|
||||
if value metadata 1 relativeto R & value eq value element 1
|
||||
r = value metadata 1 - R
|
||||
match =X?, Rw
|
||||
dw 1100b + r shl 4 + 1001001b shl 9
|
||||
else match =Y?, Rw
|
||||
dw 1000b + r shl 4 + 1000001b shl 9
|
||||
else match =Z?, Rw
|
||||
dw 0000b + r shl 4 + 1000001b shl 9
|
||||
else match =X?+, Rw
|
||||
dw 1101b + r shl 4 + 1001001b shl 9
|
||||
else match =Y?+, Rw
|
||||
dw 1001b + r shl 4 + 1001001b shl 9
|
||||
else match =Z?+, Rw
|
||||
dw 0001b + r shl 4 + 1001001b shl 9
|
||||
else match -=X?, Rw
|
||||
dw 1110b + r shl 4 + 1001001b shl 9
|
||||
else match -=Y?, Rw
|
||||
dw 1010b + r shl 4 + 1001001b shl 9
|
||||
else match -=Z?, Rw
|
||||
dw 0010b + r shl 4 + 1001001b shl 9
|
||||
else
|
||||
err 'invalid operand'
|
||||
end match
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
end macro
|
||||
|
||||
macro STD? Rq,Rr
|
||||
local value,r,q
|
||||
value = +Rr
|
||||
if value metadata 1 relativeto R & value eq value element 1
|
||||
r = value metadata 1 - R
|
||||
value = +Rq
|
||||
if value relativeto Y
|
||||
q = value - Y
|
||||
if q >= 0 & q <= 63
|
||||
dw q and 111b + 1 shl 3 + r shl 4 + 1 shl 9 + ((q shr 3) and 11b) shl 10 + (q shr 5) shl 13 + 10b shl 14
|
||||
else
|
||||
err 'value out of range'
|
||||
end if
|
||||
else if value relativeto Z
|
||||
q = value - Z
|
||||
if q >= 0 & q <= 63
|
||||
dw q and 111b + r shl 4 + 1 shl 9 + ((q shr 3) and 11b) shl 10 + (q shr 5) shl 13 + 10b shl 14
|
||||
else
|
||||
err 'value out of range'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
end macro
|
||||
|
||||
macro STS? k,Rr
|
||||
local value,r
|
||||
value = +Rr
|
||||
if value metadata 1 relativeto R & value eq value element 1
|
||||
r = value metadata 1 - R
|
||||
value = +k
|
||||
if value >= 0 & value <= 65535
|
||||
dw r shl 4 + 1001001b shl 9
|
||||
dw value
|
||||
else
|
||||
err 'address out of range'
|
||||
end if
|
||||
else
|
||||
err 'invalid operand'
|
||||
end if
|
||||
end macro
|
||||
|
||||
macro TST? Rd
|
||||
AND Rd,Rd
|
||||
end macro
|
||||
|
||||
macro WDR?
|
||||
dw 1001'0101'1010'1000b
|
||||
end macro
|
||||
|
||||
macro BREAK? %
|
||||
if defined %
|
||||
break ; loop control directive
|
||||
else
|
||||
dw 1001'0101'1001'1000b
|
||||
end if
|
||||
end macro
|
||||
|
||||
define __EVAL_BREAK eval 'break %'
|
||||
|
||||
calminstruction BREAK?
|
||||
assemble __EVAL_BREAK
|
||||
end calminstruction
|
||||
|
||||
PC? equ ($ shr 1)
|
||||
|
||||
calminstruction (label) ? definition&
|
||||
local command
|
||||
match : command?, definition
|
||||
jno other
|
||||
match :: command?, definition
|
||||
jyes other
|
||||
arrange definition, =LABEL label =AT =$ =shr 1
|
||||
assemble definition
|
||||
assemble command
|
||||
exit
|
||||
other:
|
||||
arrange definition, label definition
|
||||
assemble definition
|
||||
end calminstruction
|
||||
|
||||
if defined SRAM_START
|
||||
DSEG?.$ = SRAM_START
|
||||
else
|
||||
DSEG?.$ = 60h
|
||||
end if
|
||||
|
||||
DSEG? = 0
|
||||
|
||||
define DIRECTIVE DIRECTIVE
|
||||
|
||||
macro __ORG? addr*
|
||||
if ~ DSEG?
|
||||
org (addr) shl 1
|
||||
else
|
||||
org addr
|
||||
end if
|
||||
end macro
|
||||
DIRECTIVE.ORG? equ __ORG
|
||||
|
||||
macro __EQU? definition&
|
||||
match name == value, definition
|
||||
name? = value
|
||||
else
|
||||
err 'invalid definition'
|
||||
end match
|
||||
end macro
|
||||
DIRECTIVE.EQU? equ __EQU
|
||||
|
||||
macro __DSEG?
|
||||
if ~ DSEG?
|
||||
virtual at DSEG?.$
|
||||
DSEG? = 1
|
||||
end if
|
||||
end macro
|
||||
DIRECTIVE.DSEG? equ __DSEG
|
||||
|
||||
macro __CSEG?
|
||||
if DSEG?
|
||||
DSEG?.$ = $
|
||||
end virtual
|
||||
DSEG? = 0
|
||||
end if
|
||||
end macro
|
||||
DIRECTIVE.CSEG? equ __CSEG
|
||||
|
||||
calminstruction ? line&
|
||||
local command
|
||||
match .command, line
|
||||
jno pass
|
||||
transform command, DIRECTIVE
|
||||
jno pass
|
||||
assemble command
|
||||
exit
|
||||
pass:
|
||||
assemble line
|
||||
end calminstruction
|
||||
54
toolchain/fasmg.kl0e/examples/avr/counter.asm
Normal file
54
toolchain/fasmg.kl0e/examples/avr/counter.asm
Normal file
@ -0,0 +1,54 @@
|
||||
|
||||
; This example upon each reset increases the 8-bit counter stored in EEPROM
|
||||
; and then presents the bits of this value on the pins of port A.
|
||||
|
||||
include "avr.inc"
|
||||
include "..\8051\hex.inc"
|
||||
|
||||
include "m16def.inc"
|
||||
|
||||
.org 0
|
||||
rjmp start
|
||||
|
||||
start:
|
||||
ldi r16,RAMEND and $ff
|
||||
out spl,r16
|
||||
ldi r16,RAMEND shr 8
|
||||
out sph,r16
|
||||
|
||||
ldi r16,$37
|
||||
call eeprom_read_byte
|
||||
mov r17,r16
|
||||
inc r17
|
||||
ldi r16,$37
|
||||
call eeprom_write_byte
|
||||
|
||||
ldi r18,11111111b
|
||||
out DDRA,r18
|
||||
out PORTA,r17
|
||||
|
||||
hang: jmp hang
|
||||
|
||||
eeprom_read_byte:
|
||||
; r16 = EEPROM address
|
||||
; returns: r16 = byte data
|
||||
sbic EECR,EEWE
|
||||
jmp eeprom_read_byte
|
||||
out EEARL,r16
|
||||
sbi EECR,EERE
|
||||
in r16,EEDR
|
||||
ret
|
||||
|
||||
eeprom_write_byte:
|
||||
; r16 = EEPROM address
|
||||
; r17 = byte data
|
||||
cli
|
||||
while_eeprom_busy:
|
||||
sbic EECR,EEWE
|
||||
jmp while_eeprom_busy
|
||||
out EEARL,r16
|
||||
out EEDR,r17
|
||||
sbi EECR,EEMWE
|
||||
sbi EECR,EEWE
|
||||
sei
|
||||
ret
|
||||
738
toolchain/fasmg.kl0e/examples/avr/m16def.inc
Normal file
738
toolchain/fasmg.kl0e/examples/avr/m16def.inc
Normal file
@ -0,0 +1,738 @@
|
||||
|
||||
; Register/Bit Definitions for the ATmega16
|
||||
|
||||
; I/O Registers
|
||||
.equ SREG = 0x3f
|
||||
.equ SPH = 0x3e
|
||||
.equ SPL = 0x3d
|
||||
.equ OCR0 = 0x3c
|
||||
.equ GICR = 0x3b
|
||||
.equ GIFR = 0x3a
|
||||
.equ TIMSK = 0x39
|
||||
.equ TIFR = 0x38
|
||||
.equ SPMCSR = 0x37
|
||||
.equ TWCR = 0x36
|
||||
.equ MCUCR = 0x35
|
||||
.equ MCUCSR = 0x34
|
||||
.equ TCCR0 = 0x33
|
||||
.equ TCNT0 = 0x32
|
||||
.equ OSCCAL = 0x31
|
||||
.equ OCDR = 0x31
|
||||
.equ SFIOR = 0x30
|
||||
.equ TCCR1A = 0x2f
|
||||
.equ TCCR1B = 0x2e
|
||||
.equ TCNT1H = 0x2d
|
||||
.equ TCNT1L = 0x2c
|
||||
.equ OCR1AH = 0x2b
|
||||
.equ OCR1AL = 0x2a
|
||||
.equ OCR1BH = 0x29
|
||||
.equ OCR1BL = 0x28
|
||||
.equ ICR1H = 0x27
|
||||
.equ ICR1L = 0x26
|
||||
.equ TCCR2 = 0x25
|
||||
.equ TCNT2 = 0x24
|
||||
.equ OCR2 = 0x23
|
||||
.equ ASSR = 0x22
|
||||
.equ WDTCR = 0x21
|
||||
.equ UBRRH = 0x20
|
||||
.equ UCSRC = 0x20
|
||||
.equ EEARH = 0x1f
|
||||
.equ EEARL = 0x1e
|
||||
.equ EEDR = 0x1d
|
||||
.equ EECR = 0x1c
|
||||
.equ PORTA = 0x1b
|
||||
.equ DDRA = 0x1a
|
||||
.equ PINA = 0x19
|
||||
.equ PORTB = 0x18
|
||||
.equ DDRB = 0x17
|
||||
.equ PINB = 0x16
|
||||
.equ PORTC = 0x15
|
||||
.equ DDRC = 0x14
|
||||
.equ PINC = 0x13
|
||||
.equ PORTD = 0x12
|
||||
.equ DDRD = 0x11
|
||||
.equ PIND = 0x10
|
||||
.equ SPDR = 0x0f
|
||||
.equ SPSR = 0x0e
|
||||
.equ SPCR = 0x0d
|
||||
.equ UDR = 0x0c
|
||||
.equ UCSRA = 0x0b
|
||||
.equ UCSRB = 0x0a
|
||||
.equ UBRRL = 0x09
|
||||
.equ ACSR = 0x08
|
||||
.equ ADMUX = 0x07
|
||||
.equ ADCSRA = 0x06
|
||||
.equ ADCH = 0x05
|
||||
.equ ADCL = 0x04
|
||||
.equ TWDR = 0x03
|
||||
.equ TWAR = 0x02
|
||||
.equ TWSR = 0x01
|
||||
.equ TWBR = 0x00
|
||||
|
||||
; TCCR0 - Timer/Counter Control Register
|
||||
.equ CS00 = 0 ; Clock Select 1
|
||||
.equ CS01 = 1 ; Clock Select 1
|
||||
.equ CS02 = 2 ; Clock Select 2
|
||||
.equ WGM01 = 3 ; Waveform Generation Mode 1
|
||||
.equ CTC0 = WGM01 ; For compatibility
|
||||
.equ COM00 = 4 ; Compare match Output Mode 0
|
||||
.equ COM01 = 5 ; Compare Match Output Mode 1
|
||||
.equ WGM00 = 6 ; Waveform Generation Mode 0
|
||||
.equ PWM0 = WGM00 ; For compatibility
|
||||
.equ FOC0 = 7 ; Force Output Compare
|
||||
|
||||
; TCNT0 - Timer/Counter Register
|
||||
.equ TCNT0_0 = 0
|
||||
.equ TCNT0_1 = 1
|
||||
.equ TCNT0_2 = 2
|
||||
.equ TCNT0_3 = 3
|
||||
.equ TCNT0_4 = 4
|
||||
.equ TCNT0_5 = 5
|
||||
.equ TCNT0_6 = 6
|
||||
.equ TCNT0_7 = 7
|
||||
|
||||
; OCR0 - Output Compare Register
|
||||
.equ OCR0_0 = 0
|
||||
.equ OCR0_1 = 1
|
||||
.equ OCR0_2 = 2
|
||||
.equ OCR0_3 = 3
|
||||
.equ OCR0_4 = 4
|
||||
.equ OCR0_5 = 5
|
||||
.equ OCR0_6 = 6
|
||||
.equ OCR0_7 = 7
|
||||
|
||||
; TIMSK - Timer/Counter Interrupt Mask Register
|
||||
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
|
||||
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register
|
||||
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
|
||||
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
|
||||
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable
|
||||
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable
|
||||
|
||||
; TIFR - Timer/Counter Interrupt Flag register
|
||||
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
|
||||
.equ OCF0 = 1 ; Output Compare Flag 0
|
||||
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
|
||||
.equ OCF2 = 7 ; Output Compare Flag 2
|
||||
|
||||
; SFIOR - Special Function IO Register
|
||||
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||||
|
||||
; TIFR - Timer/Counter Interrupt Flag register
|
||||
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
|
||||
.equ OCF1B = 3 ; Output Compare Flag 1B
|
||||
.equ OCF1A = 4 ; Output Compare Flag 1A
|
||||
.equ ICF1 = 5 ; Input Capture Flag 1
|
||||
|
||||
; TCCR1A - Timer/Counter1 Control Register A
|
||||
.equ WGM10 = 0 ; Waveform Generation Mode
|
||||
.equ PWM10 = WGM10 ; For compatibility
|
||||
.equ WGM11 = 1 ; Waveform Generation Mode
|
||||
.equ PWM11 = WGM11 ; For compatibility
|
||||
.equ FOC1B = 2 ; Force Output Compare 1B
|
||||
.equ FOC1A = 3 ; Force Output Compare 1A
|
||||
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
|
||||
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
|
||||
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
|
||||
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
|
||||
|
||||
; TCCR1B - Timer/Counter1 Control Register B
|
||||
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
|
||||
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
|
||||
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
|
||||
.equ WGM12 = 3 ; Waveform Generation Mode
|
||||
.equ CTC10 = WGM12 ; For compatibility
|
||||
.equ CTC1 = WGM12 ; For compatibility
|
||||
.equ WGM13 = 4 ; Waveform Generation Mode
|
||||
.equ CTC11 = WGM13 ; For compatibility
|
||||
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
||||
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
||||
|
||||
; GICR - General Interrupt Control Register
|
||||
.equ GIMSK = GICR ; For compatibility
|
||||
.equ IVCE = 0 ; Interrupt Vector Change Enable
|
||||
.equ IVSEL = 1 ; Interrupt Vector Select
|
||||
.equ INT2 = 5 ; External Interrupt Request 2 Enable
|
||||
.equ INT0 = 6 ; External Interrupt Request 0 Enable
|
||||
.equ INT1 = 7 ; External Interrupt Request 1 Enable
|
||||
|
||||
; GIFR - General Interrupt Flag Register
|
||||
.equ INTF2 = 5 ; External Interrupt Flag 2
|
||||
.equ INTF0 = 6 ; External Interrupt Flag 0
|
||||
.equ INTF1 = 7 ; External Interrupt Flag 1
|
||||
|
||||
; MCUCR - General Interrupt Control Register
|
||||
.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
|
||||
.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
|
||||
.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0
|
||||
.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1
|
||||
|
||||
; MCUCSR - MCU Control And Status Register
|
||||
.equ ISC2 = 6 ; Interrupt Sense Control 2
|
||||
|
||||
; EEDR - EEPROM Data Register
|
||||
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
|
||||
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
|
||||
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
|
||||
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
|
||||
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
|
||||
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
|
||||
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
|
||||
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
|
||||
|
||||
; EECR - EEPROM Control Register
|
||||
.equ EERE = 0 ; EEPROM Read Enable
|
||||
.equ EEWE = 1 ; EEPROM Write Enable
|
||||
.equ EEMWE = 2 ; EEPROM Master Write Enable
|
||||
.equ EEWEE = EEMWE ; For compatibility
|
||||
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
|
||||
|
||||
; SREG - Status Register
|
||||
.equ SREG_C = 0 ; Carry Flag
|
||||
.equ SREG_Z = 1 ; Zero Flag
|
||||
.equ SREG_N = 2 ; Negative Flag
|
||||
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
||||
.equ SREG_S = 4 ; Sign Bit
|
||||
.equ SREG_H = 5 ; Half Carry Flag
|
||||
.equ SREG_T = 6 ; Bit Copy Storage
|
||||
.equ SREG_I = 7 ; Global Interrupt Enable
|
||||
|
||||
; MCUCR - MCU Control Register
|
||||
;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
|
||||
;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
|
||||
;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0
|
||||
;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1
|
||||
.equ SM0 = 4 ; Sleep Mode Select
|
||||
.equ SM1 = 5 ; Sleep Mode Select
|
||||
.equ SE = 6 ; Sleep Enable
|
||||
.equ SM2 = 7 ; Sleep Mode Select
|
||||
|
||||
; MCUCSR - MCU Control And Status Register
|
||||
.equ MCUSR = MCUCSR; For compatibility
|
||||
.equ PORF = 0 ; Power-on reset flag
|
||||
.equ EXTRF = 1 ; External Reset Flag
|
||||
.equ EXTREF = EXTRF ; For compatibility
|
||||
.equ BORF = 2 ; Brown-out Reset Flag
|
||||
.equ WDRF = 3 ; Watchdog Reset Flag
|
||||
.equ JTRF = 4 ; JTAG Reset Flag
|
||||
.equ JTD = 7 ; JTAG Interface Disable
|
||||
|
||||
; OSCCAL - Oscillator Calibration Value
|
||||
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
|
||||
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
|
||||
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
|
||||
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
|
||||
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
|
||||
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
|
||||
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
|
||||
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
|
||||
|
||||
; SFIOR - Special function I/O register
|
||||
;.equ PSR10 = 0 ; Prescaler reset
|
||||
.equ PSR2 = 1 ; Prescaler reset
|
||||
.equ PUD = 2 ; Pull-up Disable
|
||||
.equ ADHSM = 3 ; ADC High Speed Mode
|
||||
.equ ADTS0 = 5 ; ADC High Speed Mode
|
||||
.equ ADTS1 = 6 ; ADC Auto Trigger Source
|
||||
.equ ADTS2 = 7 ; ADC Auto Trigger Source
|
||||
|
||||
; TCCR2 - Timer/Counter2 Control Register
|
||||
.equ CS20 = 0 ; Clock Select bit 0
|
||||
.equ CS21 = 1 ; Clock Select bit 1
|
||||
.equ CS22 = 2 ; Clock Select bit 2
|
||||
.equ WGM21 = 3 ; Waveform Generation Mode
|
||||
.equ CTC2 = WGM21 ; For compatibility
|
||||
.equ COM20 = 4 ; Compare Output Mode bit 0
|
||||
.equ COM21 = 5 ; Compare Output Mode bit 1
|
||||
.equ WGM20 = 6 ; Waveform Genration Mode
|
||||
.equ PWM2 = WGM20 ; For compatibility
|
||||
.equ FOC2 = 7 ; Force Output Compare
|
||||
|
||||
; TCNT2 - Timer/Counter2
|
||||
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
|
||||
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
|
||||
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
|
||||
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
|
||||
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
|
||||
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
|
||||
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
|
||||
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
|
||||
|
||||
; OCR2 - Timer/Counter2 Output Compare Register
|
||||
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
|
||||
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
|
||||
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
|
||||
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
|
||||
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
|
||||
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
|
||||
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
|
||||
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
|
||||
|
||||
; ASSR - Asynchronous Status Register
|
||||
.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy
|
||||
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
|
||||
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy
|
||||
.equ AS2 = 3 ; Asynchronous Timer/counter2
|
||||
|
||||
; SFIOR - Special Function IO Register
|
||||
;.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2
|
||||
|
||||
; SPDR - SPI Data Register
|
||||
.equ SPDR0 = 0 ; SPI Data Register bit 0
|
||||
.equ SPDR1 = 1 ; SPI Data Register bit 1
|
||||
.equ SPDR2 = 2 ; SPI Data Register bit 2
|
||||
.equ SPDR3 = 3 ; SPI Data Register bit 3
|
||||
.equ SPDR4 = 4 ; SPI Data Register bit 4
|
||||
.equ SPDR5 = 5 ; SPI Data Register bit 5
|
||||
.equ SPDR6 = 6 ; SPI Data Register bit 6
|
||||
.equ SPDR7 = 7 ; SPI Data Register bit 7
|
||||
|
||||
; SPSR - SPI Status Register
|
||||
.equ SPI2X = 0 ; Double SPI Speed Bit
|
||||
.equ WCOL = 6 ; Write Collision Flag
|
||||
.equ SPIF = 7 ; SPI Interrupt Flag
|
||||
|
||||
; SPCR - SPI Control Register
|
||||
.equ SPR0 = 0 ; SPI Clock Rate Select 0
|
||||
.equ SPR1 = 1 ; SPI Clock Rate Select 1
|
||||
.equ CPHA = 2 ; Clock Phase
|
||||
.equ CPOL = 3 ; Clock polarity
|
||||
.equ MSTR = 4 ; Master/Slave Select
|
||||
.equ DORD = 5 ; Data Order
|
||||
.equ SPE = 6 ; SPI Enable
|
||||
.equ SPIE = 7 ; SPI Interrupt Enable
|
||||
|
||||
; UDR - USART I/O Data Register
|
||||
.equ UDR0 = 0 ; USART I/O Data Register bit 0
|
||||
.equ UDR1 = 1 ; USART I/O Data Register bit 1
|
||||
.equ UDR2 = 2 ; USART I/O Data Register bit 2
|
||||
.equ UDR3 = 3 ; USART I/O Data Register bit 3
|
||||
.equ UDR4 = 4 ; USART I/O Data Register bit 4
|
||||
.equ UDR5 = 5 ; USART I/O Data Register bit 5
|
||||
.equ UDR6 = 6 ; USART I/O Data Register bit 6
|
||||
.equ UDR7 = 7 ; USART I/O Data Register bit 7
|
||||
|
||||
; UCSRA - USART Control and Status Register A
|
||||
.equ USR = UCSRA ; For compatibility
|
||||
.equ MPCM = 0 ; Multi-processor Communication Mode
|
||||
.equ U2X = 1 ; Double the USART transmission speed
|
||||
.equ UPE = 2 ; Parity Error
|
||||
.equ PE = UPE ; For compatibility
|
||||
.equ DOR = 3 ; Data overRun
|
||||
.equ FE = 4 ; Framing Error
|
||||
.equ UDRE = 5 ; USART Data Register Empty
|
||||
.equ TXC = 6 ; USART Transmitt Complete
|
||||
.equ RXC = 7 ; USART Receive Complete
|
||||
|
||||
; UCSRB - USART Control and Status Register B
|
||||
.equ UCR = UCSRB ; For compatibility
|
||||
.equ TXB8 = 0 ; Transmit Data Bit 8
|
||||
.equ RXB8 = 1 ; Receive Data Bit 8
|
||||
.equ UCSZ2 = 2 ; Character Size
|
||||
.equ CHR9 = UCSZ2 ; For compatibility
|
||||
.equ TXEN = 3 ; Transmitter Enable
|
||||
.equ RXEN = 4 ; Receiver Enable
|
||||
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
|
||||
.equ TXCIE = 6 ; TX Complete Interrupt Enable
|
||||
.equ RXCIE = 7 ; RX Complete Interrupt Enable
|
||||
|
||||
; UCSRC - USART Control and Status Register C
|
||||
.equ UCPOL = 0 ; Clock Polarity
|
||||
.equ UCSZ0 = 1 ; Character Size
|
||||
.equ UCSZ1 = 2 ; Character Size
|
||||
.equ USBS = 3 ; Stop Bit Select
|
||||
.equ UPM0 = 4 ; Parity Mode Bit 0
|
||||
.equ UPM1 = 5 ; Parity Mode Bit 1
|
||||
.equ UMSEL = 6 ; USART Mode Select
|
||||
.equ URSEL = 7 ; Register Select
|
||||
|
||||
.equ UBRRHI = UBRRH ; For compatibility
|
||||
|
||||
; TWBR - TWI Bit Rate register
|
||||
.equ I2BR = TWBR ; For compatibility
|
||||
.equ TWBR0 = 0 ;
|
||||
.equ TWBR1 = 1 ;
|
||||
.equ TWBR2 = 2 ;
|
||||
.equ TWBR3 = 3 ;
|
||||
.equ TWBR4 = 4 ;
|
||||
.equ TWBR5 = 5 ;
|
||||
.equ TWBR6 = 6 ;
|
||||
.equ TWBR7 = 7 ;
|
||||
|
||||
; TWCR - TWI Control Register
|
||||
.equ I2CR = TWCR ; For compatibility
|
||||
.equ TWIE = 0 ; TWI Interrupt Enable
|
||||
.equ I2IE = TWIE ; For compatibility
|
||||
.equ TWEN = 2 ; TWI Enable Bit
|
||||
.equ I2EN = TWEN ; For compatibility
|
||||
.equ ENI2C = TWEN ; For compatibility
|
||||
.equ TWWC = 3 ; TWI Write Collition Flag
|
||||
.equ I2WC = TWWC ; For compatibility
|
||||
.equ TWSTO = 4 ; TWI Stop Condition Bit
|
||||
.equ I2STO = TWSTO ; For compatibility
|
||||
.equ TWSTA = 5 ; TWI Start Condition Bit
|
||||
.equ I2STA = TWSTA ; For compatibility
|
||||
.equ TWEA = 6 ; TWI Enable Acknowledge Bit
|
||||
.equ I2EA = TWEA ; For compatibility
|
||||
.equ TWINT = 7 ; TWI Interrupt Flag
|
||||
.equ I2INT = TWINT ; For compatibility
|
||||
|
||||
; TWSR - TWI Status Register
|
||||
.equ I2SR = TWSR ; For compatibility
|
||||
.equ TWPS0 = 0 ; TWI Prescaler
|
||||
.equ TWS0 = TWPS0 ; For compatibility
|
||||
.equ I2GCE = TWPS0 ; For compatibility
|
||||
.equ TWPS1 = 1 ; TWI Prescaler
|
||||
.equ TWS1 = TWPS1 ; For compatibility
|
||||
.equ TWS3 = 3 ; TWI Status
|
||||
.equ I2S3 = TWS3 ; For compatibility
|
||||
.equ TWS4 = 4 ; TWI Status
|
||||
.equ I2S4 = TWS4 ; For compatibility
|
||||
.equ TWS5 = 5 ; TWI Status
|
||||
.equ I2S5 = TWS5 ; For compatibility
|
||||
.equ TWS6 = 6 ; TWI Status
|
||||
.equ I2S6 = TWS6 ; For compatibility
|
||||
.equ TWS7 = 7 ; TWI Status
|
||||
.equ I2S7 = TWS7 ; For compatibility
|
||||
|
||||
; TWDR - TWI Data register
|
||||
.equ I2DR = TWDR ; For compatibility
|
||||
.equ TWD0 = 0 ; TWI Data Register Bit 0
|
||||
.equ TWD1 = 1 ; TWI Data Register Bit 1
|
||||
.equ TWD2 = 2 ; TWI Data Register Bit 2
|
||||
.equ TWD3 = 3 ; TWI Data Register Bit 3
|
||||
.equ TWD4 = 4 ; TWI Data Register Bit 4
|
||||
.equ TWD5 = 5 ; TWI Data Register Bit 5
|
||||
.equ TWD6 = 6 ; TWI Data Register Bit 6
|
||||
.equ TWD7 = 7 ; TWI Data Register Bit 7
|
||||
|
||||
; TWAR - TWI (Slave) Address register
|
||||
.equ I2AR = TWAR ; For compatibility
|
||||
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
|
||||
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
|
||||
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
|
||||
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
|
||||
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
|
||||
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
|
||||
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
|
||||
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
|
||||
|
||||
; SFIOR - Special Function IO Register
|
||||
.equ ACME = 3 ; Analog Comparator Multiplexer Enable
|
||||
|
||||
; ACSR - Analog Comparator Control And Status Register
|
||||
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
|
||||
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
|
||||
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
|
||||
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
|
||||
.equ ACI = 4 ; Analog Comparator Interrupt Flag
|
||||
.equ ACO = 5 ; Analog Compare Output
|
||||
.equ ACBG = 6 ; Analog Comparator Bandgap Select
|
||||
.equ ACD = 7 ; Analog Comparator Disable
|
||||
|
||||
; ADMUX - The ADC multiplexer Selection Register
|
||||
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
|
||||
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
|
||||
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
|
||||
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
|
||||
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
|
||||
.equ ADLAR = 5 ; Left Adjust Result
|
||||
.equ REFS0 = 6 ; Reference Selection Bit 0
|
||||
.equ REFS1 = 7 ; Reference Selection Bit 1
|
||||
|
||||
; ADCSRA - The ADC Control and Status register
|
||||
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
|
||||
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
|
||||
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
|
||||
.equ ADIE = 3 ; ADC Interrupt Enable
|
||||
.equ ADIF = 4 ; ADC Interrupt Flag
|
||||
.equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
|
||||
.equ ADFR = ADATE ; For compatibility
|
||||
.equ ADSC = 6 ; ADC Start Conversion
|
||||
.equ ADEN = 7 ; ADC Enable
|
||||
|
||||
; ADCH - ADC Data Register High Byte
|
||||
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
|
||||
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
|
||||
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
|
||||
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
|
||||
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
|
||||
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
|
||||
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
|
||||
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
|
||||
|
||||
; ADCL - ADC Data Register Low Byte
|
||||
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
|
||||
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
|
||||
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
|
||||
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
|
||||
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
|
||||
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
|
||||
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
|
||||
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
|
||||
|
||||
; OCDR - On-Chip Debug Related Register in I/O Memory
|
||||
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0
|
||||
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1
|
||||
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2
|
||||
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3
|
||||
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4
|
||||
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5
|
||||
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6
|
||||
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7
|
||||
.equ IDRD = OCDR7 ; For compatibility
|
||||
|
||||
; MCUCSR - MCU Control And Status Register
|
||||
;.equ JTRF = 4 ; JTAG Reset Flag
|
||||
;.equ JTD = 7 ; JTAG Interface Disable
|
||||
|
||||
; SPMCSR - Store Program Memory Control Register
|
||||
.equ SPMCR = SPMCSR ; For compatibility
|
||||
.equ SPMEN = 0 ; Store Program Memory Enable
|
||||
.equ PGERS = 1 ; Page Erase
|
||||
.equ PGWRT = 2 ; Page Write
|
||||
.equ BLBSET = 3 ; Boot Lock Bit Set
|
||||
.equ RWWSRE = 4 ; Read While Write section read enable
|
||||
.equ ASRE = RWWSRE ; For compatibility
|
||||
.equ RWWSB = 6 ; Read While Write Section Busy
|
||||
.equ ASB = RWWSB ; For compatibility
|
||||
.equ SPMIE = 7 ; SPM Interrupt Enable
|
||||
|
||||
; PORTA - Port A Data Register
|
||||
.equ PORTA0 = 0 ; Port A Data Register bit 0
|
||||
.equ PA0 = 0 ; For compatibility
|
||||
.equ PORTA1 = 1 ; Port A Data Register bit 1
|
||||
.equ PA1 = 1 ; For compatibility
|
||||
.equ PORTA2 = 2 ; Port A Data Register bit 2
|
||||
.equ PA2 = 2 ; For compatibility
|
||||
.equ PORTA3 = 3 ; Port A Data Register bit 3
|
||||
.equ PA3 = 3 ; For compatibility
|
||||
.equ PORTA4 = 4 ; Port A Data Register bit 4
|
||||
.equ PA4 = 4 ; For compatibility
|
||||
.equ PORTA5 = 5 ; Port A Data Register bit 5
|
||||
.equ PA5 = 5 ; For compatibility
|
||||
.equ PORTA6 = 6 ; Port A Data Register bit 6
|
||||
.equ PA6 = 6 ; For compatibility
|
||||
.equ PORTA7 = 7 ; Port A Data Register bit 7
|
||||
.equ PA7 = 7 ; For compatibility
|
||||
|
||||
; DDRA - Port A Data Direction Register
|
||||
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
|
||||
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
|
||||
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
|
||||
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
|
||||
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
|
||||
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
|
||||
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
|
||||
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
|
||||
|
||||
; PINA - Port A Input Pins
|
||||
.equ PINA0 = 0 ; Input Pins, Port A bit 0
|
||||
.equ PINA1 = 1 ; Input Pins, Port A bit 1
|
||||
.equ PINA2 = 2 ; Input Pins, Port A bit 2
|
||||
.equ PINA3 = 3 ; Input Pins, Port A bit 3
|
||||
.equ PINA4 = 4 ; Input Pins, Port A bit 4
|
||||
.equ PINA5 = 5 ; Input Pins, Port A bit 5
|
||||
.equ PINA6 = 6 ; Input Pins, Port A bit 6
|
||||
.equ PINA7 = 7 ; Input Pins, Port A bit 7
|
||||
|
||||
; PORTB - Port B Data Register
|
||||
.equ PORTB0 = 0 ; Port B Data Register bit 0
|
||||
.equ PB0 = 0 ; For compatibility
|
||||
.equ PORTB1 = 1 ; Port B Data Register bit 1
|
||||
.equ PB1 = 1 ; For compatibility
|
||||
.equ PORTB2 = 2 ; Port B Data Register bit 2
|
||||
.equ PB2 = 2 ; For compatibility
|
||||
.equ PORTB3 = 3 ; Port B Data Register bit 3
|
||||
.equ PB3 = 3 ; For compatibility
|
||||
.equ PORTB4 = 4 ; Port B Data Register bit 4
|
||||
.equ PB4 = 4 ; For compatibility
|
||||
.equ PORTB5 = 5 ; Port B Data Register bit 5
|
||||
.equ PB5 = 5 ; For compatibility
|
||||
.equ PORTB6 = 6 ; Port B Data Register bit 6
|
||||
.equ PB6 = 6 ; For compatibility
|
||||
.equ PORTB7 = 7 ; Port B Data Register bit 7
|
||||
.equ PB7 = 7 ; For compatibility
|
||||
|
||||
; DDRB - Port B Data Direction Register
|
||||
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
|
||||
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
|
||||
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
|
||||
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
|
||||
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
|
||||
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
|
||||
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
|
||||
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
|
||||
|
||||
; PINB - Port B Input Pins
|
||||
.equ PINB0 = 0 ; Port B Input Pins bit 0
|
||||
.equ PINB1 = 1 ; Port B Input Pins bit 1
|
||||
.equ PINB2 = 2 ; Port B Input Pins bit 2
|
||||
.equ PINB3 = 3 ; Port B Input Pins bit 3
|
||||
.equ PINB4 = 4 ; Port B Input Pins bit 4
|
||||
.equ PINB5 = 5 ; Port B Input Pins bit 5
|
||||
.equ PINB6 = 6 ; Port B Input Pins bit 6
|
||||
.equ PINB7 = 7 ; Port B Input Pins bit 7
|
||||
|
||||
; PORTC - Port C Data Register
|
||||
.equ PORTC0 = 0 ; Port C Data Register bit 0
|
||||
.equ PC0 = 0 ; For compatibility
|
||||
.equ PORTC1 = 1 ; Port C Data Register bit 1
|
||||
.equ PC1 = 1 ; For compatibility
|
||||
.equ PORTC2 = 2 ; Port C Data Register bit 2
|
||||
.equ PC2 = 2 ; For compatibility
|
||||
.equ PORTC3 = 3 ; Port C Data Register bit 3
|
||||
.equ PC3 = 3 ; For compatibility
|
||||
.equ PORTC4 = 4 ; Port C Data Register bit 4
|
||||
.equ PC4 = 4 ; For compatibility
|
||||
.equ PORTC5 = 5 ; Port C Data Register bit 5
|
||||
.equ PC5 = 5 ; For compatibility
|
||||
.equ PORTC6 = 6 ; Port C Data Register bit 6
|
||||
.equ PC6 = 6 ; For compatibility
|
||||
.equ PORTC7 = 7 ; Port C Data Register bit 7
|
||||
.equ PC7 = 7 ; For compatibility
|
||||
|
||||
; DDRC - Port C Data Direction Register
|
||||
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
|
||||
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
|
||||
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
|
||||
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
|
||||
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
|
||||
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
|
||||
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
|
||||
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
|
||||
|
||||
; PINC - Port C Input Pins
|
||||
.equ PINC0 = 0 ; Port C Input Pins bit 0
|
||||
.equ PINC1 = 1 ; Port C Input Pins bit 1
|
||||
.equ PINC2 = 2 ; Port C Input Pins bit 2
|
||||
.equ PINC3 = 3 ; Port C Input Pins bit 3
|
||||
.equ PINC4 = 4 ; Port C Input Pins bit 4
|
||||
.equ PINC5 = 5 ; Port C Input Pins bit 5
|
||||
.equ PINC6 = 6 ; Port C Input Pins bit 6
|
||||
.equ PINC7 = 7 ; Port C Input Pins bit 7
|
||||
|
||||
; PORTD - Port D Data Register
|
||||
.equ PORTD0 = 0 ; Port D Data Register bit 0
|
||||
.equ PD0 = 0 ; For compatibility
|
||||
.equ PORTD1 = 1 ; Port D Data Register bit 1
|
||||
.equ PD1 = 1 ; For compatibility
|
||||
.equ PORTD2 = 2 ; Port D Data Register bit 2
|
||||
.equ PD2 = 2 ; For compatibility
|
||||
.equ PORTD3 = 3 ; Port D Data Register bit 3
|
||||
.equ PD3 = 3 ; For compatibility
|
||||
.equ PORTD4 = 4 ; Port D Data Register bit 4
|
||||
.equ PD4 = 4 ; For compatibility
|
||||
.equ PORTD5 = 5 ; Port D Data Register bit 5
|
||||
.equ PD5 = 5 ; For compatibility
|
||||
.equ PORTD6 = 6 ; Port D Data Register bit 6
|
||||
.equ PD6 = 6 ; For compatibility
|
||||
.equ PORTD7 = 7 ; Port D Data Register bit 7
|
||||
.equ PD7 = 7 ; For compatibility
|
||||
|
||||
; DDRD - Port D Data Direction Register
|
||||
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
|
||||
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
|
||||
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
|
||||
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
|
||||
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
|
||||
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
|
||||
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
|
||||
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
|
||||
|
||||
; PIND - Port D Input Pins
|
||||
.equ PIND0 = 0 ; Port D Input Pins bit 0
|
||||
.equ PIND1 = 1 ; Port D Input Pins bit 1
|
||||
.equ PIND2 = 2 ; Port D Input Pins bit 2
|
||||
.equ PIND3 = 3 ; Port D Input Pins bit 3
|
||||
.equ PIND4 = 4 ; Port D Input Pins bit 4
|
||||
.equ PIND5 = 5 ; Port D Input Pins bit 5
|
||||
.equ PIND6 = 6 ; Port D Input Pins bit 6
|
||||
.equ PIND7 = 7 ; Port D Input Pins bit 7
|
||||
|
||||
; WDTCR - Watchdog Timer Control Register
|
||||
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
||||
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
||||
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
||||
.equ WDE = 3 ; Watch Dog Enable
|
||||
.equ WDTOE = 4 ; RW
|
||||
.equ WDDE = WDTOE ; For compatibility
|
||||
|
||||
; Locks Bits
|
||||
.equ LB1 = 0 ; Lock bit
|
||||
.equ LB2 = 1 ; Lock bit
|
||||
.equ BLB01 = 2 ; Boot Lock bit
|
||||
.equ BLB02 = 3 ; Boot Lock bit
|
||||
.equ BLB11 = 4 ; Boot lock bit
|
||||
.equ BLB12 = 5 ; Boot lock bit
|
||||
|
||||
; Low Fuse Bits
|
||||
.equ CKSEL0 = 0 ; Select Clock Source
|
||||
.equ CKSEL1 = 1 ; Select Clock Source
|
||||
.equ CKSEL2 = 2 ; Select Clock Source
|
||||
.equ CKSEL3 = 3 ; Select Clock Source
|
||||
.equ SUT0 = 4 ; Select start-up time
|
||||
.equ SUT1 = 5 ; Select start-up time
|
||||
.equ BODEN = 6 ; Brown out detector enable
|
||||
.equ BODLEVEL= 7 ; Brown out detector trigger level
|
||||
|
||||
; High Fuse Bits
|
||||
.equ BOOTRST = 0 ; Select Reset Vector
|
||||
.equ BOOTSZ0 = 1 ; Select Boot Size
|
||||
.equ BOOTSZ1 = 2 ; Select Boot Size
|
||||
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
|
||||
.equ CKOPT = 4 ; Oscillator Options
|
||||
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
||||
.equ JTAGEN = 6 ; Enable JTAG
|
||||
.equ OCDEN = 7 ; Enable OCD
|
||||
|
||||
; Data Memory
|
||||
.equ FLASHEND = 0x1fff ; Note: Word address
|
||||
.equ IOEND = 0x003f
|
||||
.equ SRAM_START = 0x0060
|
||||
.equ SRAM_SIZE = 1024
|
||||
.equ RAMEND = 0x045f
|
||||
.equ XRAMEND = 0x0000
|
||||
.equ E2END = 0x01ff
|
||||
.equ EEPROMEND = 0x01ff
|
||||
.equ EEADRBITS = 9
|
||||
|
||||
; Bootloader
|
||||
.equ NRWW_START_ADDR = 0x1c00
|
||||
.equ NRWW_STOP_ADDR = 0x1fff
|
||||
.equ RWW_START_ADDR = 0x0
|
||||
.equ RWW_STOP_ADDR = 0x1bff
|
||||
.equ PAGESIZE = 64
|
||||
.equ FIRSTBOOTSTART = 0x1f80
|
||||
.equ SECONDBOOTSTART = 0x1f00
|
||||
.equ THIRDBOOTSTART = 0x1e00
|
||||
.equ FOURTHBOOTSTART = 0x1c00
|
||||
.equ SMALLBOOTSTART = FIRSTBOOTSTART
|
||||
.equ LARGEBOOTSTART = FOURTHBOOTSTART
|
||||
|
||||
; Interrupt Vectors
|
||||
.equ INT0addr = 0x0002 ; External Interrupt Request 0
|
||||
.equ INT1addr = 0x0004 ; External Interrupt Request 1
|
||||
.equ OC2addr = 0x0006 ; Timer/Counter2 Compare Match
|
||||
.equ OVF2addr = 0x0008 ; Timer/Counter2 Overflow
|
||||
.equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event
|
||||
.equ OC1Aaddr = 0x000c ; Timer/Counter1 Compare Match A
|
||||
.equ OC1Baddr = 0x000e ; Timer/Counter1 Compare Match B
|
||||
.equ OVF1addr = 0x0010 ; Timer/Counter1 Overflow
|
||||
.equ OVF0addr = 0x0012 ; Timer/Counter0 Overflow
|
||||
.equ SPIaddr = 0x0014 ; Serial Transfer Complete
|
||||
.equ URXCaddr = 0x0016 ; USART, Rx Complete
|
||||
.equ UDREaddr = 0x0018 ; USART Data Register Empty
|
||||
.equ UTXCaddr = 0x001a ; USART, Tx Complete
|
||||
.equ ADCCaddr = 0x001c ; ADC Conversion Complete
|
||||
.equ ERDYaddr = 0x001e ; EEPROM Ready
|
||||
.equ ACIaddr = 0x0020 ; Analog Comparator
|
||||
.equ TWIaddr = 0x0022 ; 2-wire Serial Interface
|
||||
.equ INT2addr = 0x0024 ; External Interrupt Request 2
|
||||
.equ OC0addr = 0x0026 ; Timer/Counter0 Compare Match
|
||||
.equ SPMRaddr = 0x0028 ; Store Program Memory Ready
|
||||
|
||||
.equ INT_VECTORS_SIZE = 42 ; size in words
|
||||
|
||||
1
toolchain/fasmg.kl0e/examples/avr/make.cmd
Normal file
1
toolchain/fasmg.kl0e/examples/avr/make.cmd
Normal file
@ -0,0 +1 @@
|
||||
fasmg counter.asm counter.hex
|
||||
Reference in New Issue
Block a user