739 lines
25 KiB
PHP
739 lines
25 KiB
PHP
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||
|
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; Register/Bit Definitions for the ATmega16
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; I/O Registers
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.equ SREG = 0x3f
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.equ SPH = 0x3e
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.equ SPL = 0x3d
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.equ OCR0 = 0x3c
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.equ GICR = 0x3b
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.equ GIFR = 0x3a
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.equ TIMSK = 0x39
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.equ TIFR = 0x38
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.equ SPMCSR = 0x37
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.equ TWCR = 0x36
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.equ MCUCR = 0x35
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.equ MCUCSR = 0x34
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.equ TCCR0 = 0x33
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.equ TCNT0 = 0x32
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.equ OSCCAL = 0x31
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.equ OCDR = 0x31
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.equ SFIOR = 0x30
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.equ TCCR1A = 0x2f
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.equ TCCR1B = 0x2e
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.equ TCNT1H = 0x2d
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.equ TCNT1L = 0x2c
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.equ OCR1AH = 0x2b
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.equ OCR1AL = 0x2a
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.equ OCR1BH = 0x29
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.equ OCR1BL = 0x28
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.equ ICR1H = 0x27
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.equ ICR1L = 0x26
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.equ TCCR2 = 0x25
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.equ TCNT2 = 0x24
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.equ OCR2 = 0x23
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.equ ASSR = 0x22
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.equ WDTCR = 0x21
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.equ UBRRH = 0x20
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.equ UCSRC = 0x20
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.equ EEARH = 0x1f
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.equ EEARL = 0x1e
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.equ EEDR = 0x1d
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.equ EECR = 0x1c
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.equ PORTA = 0x1b
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.equ DDRA = 0x1a
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.equ PINA = 0x19
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.equ PORTB = 0x18
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.equ DDRB = 0x17
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.equ PINB = 0x16
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.equ PORTC = 0x15
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.equ DDRC = 0x14
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.equ PINC = 0x13
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.equ PORTD = 0x12
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.equ DDRD = 0x11
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.equ PIND = 0x10
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.equ SPDR = 0x0f
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.equ SPSR = 0x0e
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.equ SPCR = 0x0d
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.equ UDR = 0x0c
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.equ UCSRA = 0x0b
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.equ UCSRB = 0x0a
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.equ UBRRL = 0x09
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.equ ACSR = 0x08
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.equ ADMUX = 0x07
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.equ ADCSRA = 0x06
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.equ ADCH = 0x05
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.equ ADCL = 0x04
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.equ TWDR = 0x03
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.equ TWAR = 0x02
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.equ TWSR = 0x01
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.equ TWBR = 0x00
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; TCCR0 - Timer/Counter Control Register
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.equ CS00 = 0 ; Clock Select 1
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.equ CS01 = 1 ; Clock Select 1
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.equ CS02 = 2 ; Clock Select 2
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.equ WGM01 = 3 ; Waveform Generation Mode 1
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.equ CTC0 = WGM01 ; For compatibility
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.equ COM00 = 4 ; Compare match Output Mode 0
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.equ COM01 = 5 ; Compare Match Output Mode 1
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.equ WGM00 = 6 ; Waveform Generation Mode 0
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.equ PWM0 = WGM00 ; For compatibility
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.equ FOC0 = 7 ; Force Output Compare
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; TCNT0 - Timer/Counter Register
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.equ TCNT0_0 = 0
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.equ TCNT0_1 = 1
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.equ TCNT0_2 = 2
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.equ TCNT0_3 = 3
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.equ TCNT0_4 = 4
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.equ TCNT0_5 = 5
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.equ TCNT0_6 = 6
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.equ TCNT0_7 = 7
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; OCR0 - Output Compare Register
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.equ OCR0_0 = 0
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.equ OCR0_1 = 1
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.equ OCR0_2 = 2
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.equ OCR0_3 = 3
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.equ OCR0_4 = 4
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.equ OCR0_5 = 5
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.equ OCR0_6 = 6
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.equ OCR0_7 = 7
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; TIMSK - Timer/Counter Interrupt Mask Register
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.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
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.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register
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.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
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.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
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.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
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.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
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.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable
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.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable
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; TIFR - Timer/Counter Interrupt Flag register
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.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
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.equ OCF0 = 1 ; Output Compare Flag 0
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.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
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.equ OCF2 = 7 ; Output Compare Flag 2
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; SFIOR - Special Function IO Register
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.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
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; TIFR - Timer/Counter Interrupt Flag register
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.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
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.equ OCF1B = 3 ; Output Compare Flag 1B
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.equ OCF1A = 4 ; Output Compare Flag 1A
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.equ ICF1 = 5 ; Input Capture Flag 1
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; TCCR1A - Timer/Counter1 Control Register A
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.equ WGM10 = 0 ; Waveform Generation Mode
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.equ PWM10 = WGM10 ; For compatibility
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.equ WGM11 = 1 ; Waveform Generation Mode
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.equ PWM11 = WGM11 ; For compatibility
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.equ FOC1B = 2 ; Force Output Compare 1B
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.equ FOC1A = 3 ; Force Output Compare 1A
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.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
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.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
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.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
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.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
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; TCCR1B - Timer/Counter1 Control Register B
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.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
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.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
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.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
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.equ WGM12 = 3 ; Waveform Generation Mode
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.equ CTC10 = WGM12 ; For compatibility
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.equ CTC1 = WGM12 ; For compatibility
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.equ WGM13 = 4 ; Waveform Generation Mode
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.equ CTC11 = WGM13 ; For compatibility
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.equ ICES1 = 6 ; Input Capture 1 Edge Select
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.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
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; GICR - General Interrupt Control Register
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.equ GIMSK = GICR ; For compatibility
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.equ IVCE = 0 ; Interrupt Vector Change Enable
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.equ IVSEL = 1 ; Interrupt Vector Select
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.equ INT2 = 5 ; External Interrupt Request 2 Enable
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.equ INT0 = 6 ; External Interrupt Request 0 Enable
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.equ INT1 = 7 ; External Interrupt Request 1 Enable
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; GIFR - General Interrupt Flag Register
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.equ INTF2 = 5 ; External Interrupt Flag 2
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.equ INTF0 = 6 ; External Interrupt Flag 0
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.equ INTF1 = 7 ; External Interrupt Flag 1
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; MCUCR - General Interrupt Control Register
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.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
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.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
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.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0
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.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1
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; MCUCSR - MCU Control And Status Register
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.equ ISC2 = 6 ; Interrupt Sense Control 2
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; EEDR - EEPROM Data Register
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.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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; EECR - EEPROM Control Register
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.equ EERE = 0 ; EEPROM Read Enable
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.equ EEWE = 1 ; EEPROM Write Enable
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.equ EEMWE = 2 ; EEPROM Master Write Enable
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.equ EEWEE = EEMWE ; For compatibility
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.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
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; SREG - Status Register
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.equ SREG_C = 0 ; Carry Flag
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.equ SREG_Z = 1 ; Zero Flag
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.equ SREG_N = 2 ; Negative Flag
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.equ SREG_V = 3 ; Two's Complement Overflow Flag
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.equ SREG_S = 4 ; Sign Bit
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.equ SREG_H = 5 ; Half Carry Flag
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.equ SREG_T = 6 ; Bit Copy Storage
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.equ SREG_I = 7 ; Global Interrupt Enable
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; MCUCR - MCU Control Register
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;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
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;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
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;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0
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;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1
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.equ SM0 = 4 ; Sleep Mode Select
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.equ SM1 = 5 ; Sleep Mode Select
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.equ SE = 6 ; Sleep Enable
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.equ SM2 = 7 ; Sleep Mode Select
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; MCUCSR - MCU Control And Status Register
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.equ MCUSR = MCUCSR; For compatibility
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.equ PORF = 0 ; Power-on reset flag
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.equ EXTRF = 1 ; External Reset Flag
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.equ EXTREF = EXTRF ; For compatibility
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.equ BORF = 2 ; Brown-out Reset Flag
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.equ WDRF = 3 ; Watchdog Reset Flag
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.equ JTRF = 4 ; JTAG Reset Flag
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.equ JTD = 7 ; JTAG Interface Disable
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; OSCCAL - Oscillator Calibration Value
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.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
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.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
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.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
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.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
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.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
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.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
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.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
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.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
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; SFIOR - Special function I/O register
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;.equ PSR10 = 0 ; Prescaler reset
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.equ PSR2 = 1 ; Prescaler reset
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.equ PUD = 2 ; Pull-up Disable
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.equ ADHSM = 3 ; ADC High Speed Mode
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.equ ADTS0 = 5 ; ADC High Speed Mode
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.equ ADTS1 = 6 ; ADC Auto Trigger Source
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.equ ADTS2 = 7 ; ADC Auto Trigger Source
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; TCCR2 - Timer/Counter2 Control Register
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.equ CS20 = 0 ; Clock Select bit 0
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.equ CS21 = 1 ; Clock Select bit 1
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.equ CS22 = 2 ; Clock Select bit 2
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.equ WGM21 = 3 ; Waveform Generation Mode
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.equ CTC2 = WGM21 ; For compatibility
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.equ COM20 = 4 ; Compare Output Mode bit 0
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.equ COM21 = 5 ; Compare Output Mode bit 1
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.equ WGM20 = 6 ; Waveform Genration Mode
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.equ PWM2 = WGM20 ; For compatibility
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.equ FOC2 = 7 ; Force Output Compare
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; TCNT2 - Timer/Counter2
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.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
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.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
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.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
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.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
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.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
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.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
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.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
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.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
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; OCR2 - Timer/Counter2 Output Compare Register
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.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
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.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
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.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
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.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
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.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
|
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.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
|
||
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.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
|
||
|
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.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
|
||
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; ASSR - Asynchronous Status Register
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|
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.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy
|
||
|
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.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
|
||
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.equ TCN2UB = 2 ; Timer/Counter2 Update Busy
|
||
|
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.equ AS2 = 3 ; Asynchronous Timer/counter2
|
||
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|
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; SFIOR - Special Function IO Register
|
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;.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2
|
||
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|
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|
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; SPDR - SPI Data Register
|
||
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.equ SPDR0 = 0 ; SPI Data Register bit 0
|
||
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.equ SPDR1 = 1 ; SPI Data Register bit 1
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.equ SPDR2 = 2 ; SPI Data Register bit 2
|
||
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.equ SPDR3 = 3 ; SPI Data Register bit 3
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.equ SPDR4 = 4 ; SPI Data Register bit 4
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.equ SPDR5 = 5 ; SPI Data Register bit 5
|
||
|
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.equ SPDR6 = 6 ; SPI Data Register bit 6
|
||
|
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.equ SPDR7 = 7 ; SPI Data Register bit 7
|
||
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|
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|
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; SPSR - SPI Status Register
|
||
|
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.equ SPI2X = 0 ; Double SPI Speed Bit
|
||
|
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.equ WCOL = 6 ; Write Collision Flag
|
||
|
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.equ SPIF = 7 ; SPI Interrupt Flag
|
||
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|
||
|
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; SPCR - SPI Control Register
|
||
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.equ SPR0 = 0 ; SPI Clock Rate Select 0
|
||
|
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.equ SPR1 = 1 ; SPI Clock Rate Select 1
|
||
|
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.equ CPHA = 2 ; Clock Phase
|
||
|
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.equ CPOL = 3 ; Clock polarity
|
||
|
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.equ MSTR = 4 ; Master/Slave Select
|
||
|
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.equ DORD = 5 ; Data Order
|
||
|
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.equ SPE = 6 ; SPI Enable
|
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.equ SPIE = 7 ; SPI Interrupt Enable
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||
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; UDR - USART I/O Data Register
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.equ UDR0 = 0 ; USART I/O Data Register bit 0
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.equ UDR1 = 1 ; USART I/O Data Register bit 1
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.equ UDR2 = 2 ; USART I/O Data Register bit 2
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.equ UDR3 = 3 ; USART I/O Data Register bit 3
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.equ UDR4 = 4 ; USART I/O Data Register bit 4
|
||
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.equ UDR5 = 5 ; USART I/O Data Register bit 5
|
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.equ UDR6 = 6 ; USART I/O Data Register bit 6
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.equ UDR7 = 7 ; USART I/O Data Register bit 7
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||
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|
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; UCSRA - USART Control and Status Register A
|
||
|
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.equ USR = UCSRA ; For compatibility
|
||
|
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.equ MPCM = 0 ; Multi-processor Communication Mode
|
||
|
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.equ U2X = 1 ; Double the USART transmission speed
|
||
|
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.equ UPE = 2 ; Parity Error
|
||
|
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.equ PE = UPE ; For compatibility
|
||
|
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.equ DOR = 3 ; Data overRun
|
||
|
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.equ FE = 4 ; Framing Error
|
||
|
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.equ UDRE = 5 ; USART Data Register Empty
|
||
|
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.equ TXC = 6 ; USART Transmitt Complete
|
||
|
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.equ RXC = 7 ; USART Receive Complete
|
||
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|
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|
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; UCSRB - USART Control and Status Register B
|
||
|
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.equ UCR = UCSRB ; For compatibility
|
||
|
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.equ TXB8 = 0 ; Transmit Data Bit 8
|
||
|
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.equ RXB8 = 1 ; Receive Data Bit 8
|
||
|
|
.equ UCSZ2 = 2 ; Character Size
|
||
|
|
.equ CHR9 = UCSZ2 ; For compatibility
|
||
|
|
.equ TXEN = 3 ; Transmitter Enable
|
||
|
|
.equ RXEN = 4 ; Receiver Enable
|
||
|
|
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
|
||
|
|
.equ TXCIE = 6 ; TX Complete Interrupt Enable
|
||
|
|
.equ RXCIE = 7 ; RX Complete Interrupt Enable
|
||
|
|
|
||
|
|
; UCSRC - USART Control and Status Register C
|
||
|
|
.equ UCPOL = 0 ; Clock Polarity
|
||
|
|
.equ UCSZ0 = 1 ; Character Size
|
||
|
|
.equ UCSZ1 = 2 ; Character Size
|
||
|
|
.equ USBS = 3 ; Stop Bit Select
|
||
|
|
.equ UPM0 = 4 ; Parity Mode Bit 0
|
||
|
|
.equ UPM1 = 5 ; Parity Mode Bit 1
|
||
|
|
.equ UMSEL = 6 ; USART Mode Select
|
||
|
|
.equ URSEL = 7 ; Register Select
|
||
|
|
|
||
|
|
.equ UBRRHI = UBRRH ; For compatibility
|
||
|
|
|
||
|
|
; TWBR - TWI Bit Rate register
|
||
|
|
.equ I2BR = TWBR ; For compatibility
|
||
|
|
.equ TWBR0 = 0 ;
|
||
|
|
.equ TWBR1 = 1 ;
|
||
|
|
.equ TWBR2 = 2 ;
|
||
|
|
.equ TWBR3 = 3 ;
|
||
|
|
.equ TWBR4 = 4 ;
|
||
|
|
.equ TWBR5 = 5 ;
|
||
|
|
.equ TWBR6 = 6 ;
|
||
|
|
.equ TWBR7 = 7 ;
|
||
|
|
|
||
|
|
; TWCR - TWI Control Register
|
||
|
|
.equ I2CR = TWCR ; For compatibility
|
||
|
|
.equ TWIE = 0 ; TWI Interrupt Enable
|
||
|
|
.equ I2IE = TWIE ; For compatibility
|
||
|
|
.equ TWEN = 2 ; TWI Enable Bit
|
||
|
|
.equ I2EN = TWEN ; For compatibility
|
||
|
|
.equ ENI2C = TWEN ; For compatibility
|
||
|
|
.equ TWWC = 3 ; TWI Write Collition Flag
|
||
|
|
.equ I2WC = TWWC ; For compatibility
|
||
|
|
.equ TWSTO = 4 ; TWI Stop Condition Bit
|
||
|
|
.equ I2STO = TWSTO ; For compatibility
|
||
|
|
.equ TWSTA = 5 ; TWI Start Condition Bit
|
||
|
|
.equ I2STA = TWSTA ; For compatibility
|
||
|
|
.equ TWEA = 6 ; TWI Enable Acknowledge Bit
|
||
|
|
.equ I2EA = TWEA ; For compatibility
|
||
|
|
.equ TWINT = 7 ; TWI Interrupt Flag
|
||
|
|
.equ I2INT = TWINT ; For compatibility
|
||
|
|
|
||
|
|
; TWSR - TWI Status Register
|
||
|
|
.equ I2SR = TWSR ; For compatibility
|
||
|
|
.equ TWPS0 = 0 ; TWI Prescaler
|
||
|
|
.equ TWS0 = TWPS0 ; For compatibility
|
||
|
|
.equ I2GCE = TWPS0 ; For compatibility
|
||
|
|
.equ TWPS1 = 1 ; TWI Prescaler
|
||
|
|
.equ TWS1 = TWPS1 ; For compatibility
|
||
|
|
.equ TWS3 = 3 ; TWI Status
|
||
|
|
.equ I2S3 = TWS3 ; For compatibility
|
||
|
|
.equ TWS4 = 4 ; TWI Status
|
||
|
|
.equ I2S4 = TWS4 ; For compatibility
|
||
|
|
.equ TWS5 = 5 ; TWI Status
|
||
|
|
.equ I2S5 = TWS5 ; For compatibility
|
||
|
|
.equ TWS6 = 6 ; TWI Status
|
||
|
|
.equ I2S6 = TWS6 ; For compatibility
|
||
|
|
.equ TWS7 = 7 ; TWI Status
|
||
|
|
.equ I2S7 = TWS7 ; For compatibility
|
||
|
|
|
||
|
|
; TWDR - TWI Data register
|
||
|
|
.equ I2DR = TWDR ; For compatibility
|
||
|
|
.equ TWD0 = 0 ; TWI Data Register Bit 0
|
||
|
|
.equ TWD1 = 1 ; TWI Data Register Bit 1
|
||
|
|
.equ TWD2 = 2 ; TWI Data Register Bit 2
|
||
|
|
.equ TWD3 = 3 ; TWI Data Register Bit 3
|
||
|
|
.equ TWD4 = 4 ; TWI Data Register Bit 4
|
||
|
|
.equ TWD5 = 5 ; TWI Data Register Bit 5
|
||
|
|
.equ TWD6 = 6 ; TWI Data Register Bit 6
|
||
|
|
.equ TWD7 = 7 ; TWI Data Register Bit 7
|
||
|
|
|
||
|
|
; TWAR - TWI (Slave) Address register
|
||
|
|
.equ I2AR = TWAR ; For compatibility
|
||
|
|
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
|
||
|
|
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
|
||
|
|
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
|
||
|
|
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
|
||
|
|
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
|
||
|
|
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
|
||
|
|
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
|
||
|
|
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
|
||
|
|
|
||
|
|
; SFIOR - Special Function IO Register
|
||
|
|
.equ ACME = 3 ; Analog Comparator Multiplexer Enable
|
||
|
|
|
||
|
|
; ACSR - Analog Comparator Control And Status Register
|
||
|
|
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
|
||
|
|
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
|
||
|
|
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
|
||
|
|
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
|
||
|
|
.equ ACI = 4 ; Analog Comparator Interrupt Flag
|
||
|
|
.equ ACO = 5 ; Analog Compare Output
|
||
|
|
.equ ACBG = 6 ; Analog Comparator Bandgap Select
|
||
|
|
.equ ACD = 7 ; Analog Comparator Disable
|
||
|
|
|
||
|
|
; ADMUX - The ADC multiplexer Selection Register
|
||
|
|
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
|
||
|
|
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
|
||
|
|
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
|
||
|
|
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
|
||
|
|
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
|
||
|
|
.equ ADLAR = 5 ; Left Adjust Result
|
||
|
|
.equ REFS0 = 6 ; Reference Selection Bit 0
|
||
|
|
.equ REFS1 = 7 ; Reference Selection Bit 1
|
||
|
|
|
||
|
|
; ADCSRA - The ADC Control and Status register
|
||
|
|
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
|
||
|
|
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
|
||
|
|
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
|
||
|
|
.equ ADIE = 3 ; ADC Interrupt Enable
|
||
|
|
.equ ADIF = 4 ; ADC Interrupt Flag
|
||
|
|
.equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
|
||
|
|
.equ ADFR = ADATE ; For compatibility
|
||
|
|
.equ ADSC = 6 ; ADC Start Conversion
|
||
|
|
.equ ADEN = 7 ; ADC Enable
|
||
|
|
|
||
|
|
; ADCH - ADC Data Register High Byte
|
||
|
|
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
|
||
|
|
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
|
||
|
|
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
|
||
|
|
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
|
||
|
|
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
|
||
|
|
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
|
||
|
|
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
|
||
|
|
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
|
||
|
|
|
||
|
|
; ADCL - ADC Data Register Low Byte
|
||
|
|
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
|
||
|
|
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
|
||
|
|
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
|
||
|
|
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
|
||
|
|
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
|
||
|
|
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
|
||
|
|
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
|
||
|
|
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
|
||
|
|
|
||
|
|
; OCDR - On-Chip Debug Related Register in I/O Memory
|
||
|
|
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0
|
||
|
|
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1
|
||
|
|
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2
|
||
|
|
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3
|
||
|
|
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4
|
||
|
|
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5
|
||
|
|
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6
|
||
|
|
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7
|
||
|
|
.equ IDRD = OCDR7 ; For compatibility
|
||
|
|
|
||
|
|
; MCUCSR - MCU Control And Status Register
|
||
|
|
;.equ JTRF = 4 ; JTAG Reset Flag
|
||
|
|
;.equ JTD = 7 ; JTAG Interface Disable
|
||
|
|
|
||
|
|
; SPMCSR - Store Program Memory Control Register
|
||
|
|
.equ SPMCR = SPMCSR ; For compatibility
|
||
|
|
.equ SPMEN = 0 ; Store Program Memory Enable
|
||
|
|
.equ PGERS = 1 ; Page Erase
|
||
|
|
.equ PGWRT = 2 ; Page Write
|
||
|
|
.equ BLBSET = 3 ; Boot Lock Bit Set
|
||
|
|
.equ RWWSRE = 4 ; Read While Write section read enable
|
||
|
|
.equ ASRE = RWWSRE ; For compatibility
|
||
|
|
.equ RWWSB = 6 ; Read While Write Section Busy
|
||
|
|
.equ ASB = RWWSB ; For compatibility
|
||
|
|
.equ SPMIE = 7 ; SPM Interrupt Enable
|
||
|
|
|
||
|
|
; PORTA - Port A Data Register
|
||
|
|
.equ PORTA0 = 0 ; Port A Data Register bit 0
|
||
|
|
.equ PA0 = 0 ; For compatibility
|
||
|
|
.equ PORTA1 = 1 ; Port A Data Register bit 1
|
||
|
|
.equ PA1 = 1 ; For compatibility
|
||
|
|
.equ PORTA2 = 2 ; Port A Data Register bit 2
|
||
|
|
.equ PA2 = 2 ; For compatibility
|
||
|
|
.equ PORTA3 = 3 ; Port A Data Register bit 3
|
||
|
|
.equ PA3 = 3 ; For compatibility
|
||
|
|
.equ PORTA4 = 4 ; Port A Data Register bit 4
|
||
|
|
.equ PA4 = 4 ; For compatibility
|
||
|
|
.equ PORTA5 = 5 ; Port A Data Register bit 5
|
||
|
|
.equ PA5 = 5 ; For compatibility
|
||
|
|
.equ PORTA6 = 6 ; Port A Data Register bit 6
|
||
|
|
.equ PA6 = 6 ; For compatibility
|
||
|
|
.equ PORTA7 = 7 ; Port A Data Register bit 7
|
||
|
|
.equ PA7 = 7 ; For compatibility
|
||
|
|
|
||
|
|
; DDRA - Port A Data Direction Register
|
||
|
|
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
|
||
|
|
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
|
||
|
|
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
|
||
|
|
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
|
||
|
|
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
|
||
|
|
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
|
||
|
|
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
|
||
|
|
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
|
||
|
|
|
||
|
|
; PINA - Port A Input Pins
|
||
|
|
.equ PINA0 = 0 ; Input Pins, Port A bit 0
|
||
|
|
.equ PINA1 = 1 ; Input Pins, Port A bit 1
|
||
|
|
.equ PINA2 = 2 ; Input Pins, Port A bit 2
|
||
|
|
.equ PINA3 = 3 ; Input Pins, Port A bit 3
|
||
|
|
.equ PINA4 = 4 ; Input Pins, Port A bit 4
|
||
|
|
.equ PINA5 = 5 ; Input Pins, Port A bit 5
|
||
|
|
.equ PINA6 = 6 ; Input Pins, Port A bit 6
|
||
|
|
.equ PINA7 = 7 ; Input Pins, Port A bit 7
|
||
|
|
|
||
|
|
; PORTB - Port B Data Register
|
||
|
|
.equ PORTB0 = 0 ; Port B Data Register bit 0
|
||
|
|
.equ PB0 = 0 ; For compatibility
|
||
|
|
.equ PORTB1 = 1 ; Port B Data Register bit 1
|
||
|
|
.equ PB1 = 1 ; For compatibility
|
||
|
|
.equ PORTB2 = 2 ; Port B Data Register bit 2
|
||
|
|
.equ PB2 = 2 ; For compatibility
|
||
|
|
.equ PORTB3 = 3 ; Port B Data Register bit 3
|
||
|
|
.equ PB3 = 3 ; For compatibility
|
||
|
|
.equ PORTB4 = 4 ; Port B Data Register bit 4
|
||
|
|
.equ PB4 = 4 ; For compatibility
|
||
|
|
.equ PORTB5 = 5 ; Port B Data Register bit 5
|
||
|
|
.equ PB5 = 5 ; For compatibility
|
||
|
|
.equ PORTB6 = 6 ; Port B Data Register bit 6
|
||
|
|
.equ PB6 = 6 ; For compatibility
|
||
|
|
.equ PORTB7 = 7 ; Port B Data Register bit 7
|
||
|
|
.equ PB7 = 7 ; For compatibility
|
||
|
|
|
||
|
|
; DDRB - Port B Data Direction Register
|
||
|
|
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
|
||
|
|
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
|
||
|
|
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
|
||
|
|
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
|
||
|
|
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
|
||
|
|
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
|
||
|
|
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
|
||
|
|
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
|
||
|
|
|
||
|
|
; PINB - Port B Input Pins
|
||
|
|
.equ PINB0 = 0 ; Port B Input Pins bit 0
|
||
|
|
.equ PINB1 = 1 ; Port B Input Pins bit 1
|
||
|
|
.equ PINB2 = 2 ; Port B Input Pins bit 2
|
||
|
|
.equ PINB3 = 3 ; Port B Input Pins bit 3
|
||
|
|
.equ PINB4 = 4 ; Port B Input Pins bit 4
|
||
|
|
.equ PINB5 = 5 ; Port B Input Pins bit 5
|
||
|
|
.equ PINB6 = 6 ; Port B Input Pins bit 6
|
||
|
|
.equ PINB7 = 7 ; Port B Input Pins bit 7
|
||
|
|
|
||
|
|
; PORTC - Port C Data Register
|
||
|
|
.equ PORTC0 = 0 ; Port C Data Register bit 0
|
||
|
|
.equ PC0 = 0 ; For compatibility
|
||
|
|
.equ PORTC1 = 1 ; Port C Data Register bit 1
|
||
|
|
.equ PC1 = 1 ; For compatibility
|
||
|
|
.equ PORTC2 = 2 ; Port C Data Register bit 2
|
||
|
|
.equ PC2 = 2 ; For compatibility
|
||
|
|
.equ PORTC3 = 3 ; Port C Data Register bit 3
|
||
|
|
.equ PC3 = 3 ; For compatibility
|
||
|
|
.equ PORTC4 = 4 ; Port C Data Register bit 4
|
||
|
|
.equ PC4 = 4 ; For compatibility
|
||
|
|
.equ PORTC5 = 5 ; Port C Data Register bit 5
|
||
|
|
.equ PC5 = 5 ; For compatibility
|
||
|
|
.equ PORTC6 = 6 ; Port C Data Register bit 6
|
||
|
|
.equ PC6 = 6 ; For compatibility
|
||
|
|
.equ PORTC7 = 7 ; Port C Data Register bit 7
|
||
|
|
.equ PC7 = 7 ; For compatibility
|
||
|
|
|
||
|
|
; DDRC - Port C Data Direction Register
|
||
|
|
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
|
||
|
|
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
|
||
|
|
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
|
||
|
|
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
|
||
|
|
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
|
||
|
|
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
|
||
|
|
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
|
||
|
|
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
|
||
|
|
|
||
|
|
; PINC - Port C Input Pins
|
||
|
|
.equ PINC0 = 0 ; Port C Input Pins bit 0
|
||
|
|
.equ PINC1 = 1 ; Port C Input Pins bit 1
|
||
|
|
.equ PINC2 = 2 ; Port C Input Pins bit 2
|
||
|
|
.equ PINC3 = 3 ; Port C Input Pins bit 3
|
||
|
|
.equ PINC4 = 4 ; Port C Input Pins bit 4
|
||
|
|
.equ PINC5 = 5 ; Port C Input Pins bit 5
|
||
|
|
.equ PINC6 = 6 ; Port C Input Pins bit 6
|
||
|
|
.equ PINC7 = 7 ; Port C Input Pins bit 7
|
||
|
|
|
||
|
|
; PORTD - Port D Data Register
|
||
|
|
.equ PORTD0 = 0 ; Port D Data Register bit 0
|
||
|
|
.equ PD0 = 0 ; For compatibility
|
||
|
|
.equ PORTD1 = 1 ; Port D Data Register bit 1
|
||
|
|
.equ PD1 = 1 ; For compatibility
|
||
|
|
.equ PORTD2 = 2 ; Port D Data Register bit 2
|
||
|
|
.equ PD2 = 2 ; For compatibility
|
||
|
|
.equ PORTD3 = 3 ; Port D Data Register bit 3
|
||
|
|
.equ PD3 = 3 ; For compatibility
|
||
|
|
.equ PORTD4 = 4 ; Port D Data Register bit 4
|
||
|
|
.equ PD4 = 4 ; For compatibility
|
||
|
|
.equ PORTD5 = 5 ; Port D Data Register bit 5
|
||
|
|
.equ PD5 = 5 ; For compatibility
|
||
|
|
.equ PORTD6 = 6 ; Port D Data Register bit 6
|
||
|
|
.equ PD6 = 6 ; For compatibility
|
||
|
|
.equ PORTD7 = 7 ; Port D Data Register bit 7
|
||
|
|
.equ PD7 = 7 ; For compatibility
|
||
|
|
|
||
|
|
; DDRD - Port D Data Direction Register
|
||
|
|
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
|
||
|
|
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
|
||
|
|
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
|
||
|
|
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
|
||
|
|
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
|
||
|
|
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
|
||
|
|
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
|
||
|
|
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
|
||
|
|
|
||
|
|
; PIND - Port D Input Pins
|
||
|
|
.equ PIND0 = 0 ; Port D Input Pins bit 0
|
||
|
|
.equ PIND1 = 1 ; Port D Input Pins bit 1
|
||
|
|
.equ PIND2 = 2 ; Port D Input Pins bit 2
|
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.equ PIND3 = 3 ; Port D Input Pins bit 3
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.equ PIND4 = 4 ; Port D Input Pins bit 4
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.equ PIND5 = 5 ; Port D Input Pins bit 5
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.equ PIND6 = 6 ; Port D Input Pins bit 6
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.equ PIND7 = 7 ; Port D Input Pins bit 7
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; WDTCR - Watchdog Timer Control Register
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.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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.equ WDE = 3 ; Watch Dog Enable
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||
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.equ WDTOE = 4 ; RW
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||
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.equ WDDE = WDTOE ; For compatibility
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||
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||
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; Locks Bits
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||
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.equ LB1 = 0 ; Lock bit
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||
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.equ LB2 = 1 ; Lock bit
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||
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.equ BLB01 = 2 ; Boot Lock bit
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||
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.equ BLB02 = 3 ; Boot Lock bit
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||
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.equ BLB11 = 4 ; Boot lock bit
|
||
|
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.equ BLB12 = 5 ; Boot lock bit
|
||
|
|
|
||
|
|
; Low Fuse Bits
|
||
|
|
.equ CKSEL0 = 0 ; Select Clock Source
|
||
|
|
.equ CKSEL1 = 1 ; Select Clock Source
|
||
|
|
.equ CKSEL2 = 2 ; Select Clock Source
|
||
|
|
.equ CKSEL3 = 3 ; Select Clock Source
|
||
|
|
.equ SUT0 = 4 ; Select start-up time
|
||
|
|
.equ SUT1 = 5 ; Select start-up time
|
||
|
|
.equ BODEN = 6 ; Brown out detector enable
|
||
|
|
.equ BODLEVEL= 7 ; Brown out detector trigger level
|
||
|
|
|
||
|
|
; High Fuse Bits
|
||
|
|
.equ BOOTRST = 0 ; Select Reset Vector
|
||
|
|
.equ BOOTSZ0 = 1 ; Select Boot Size
|
||
|
|
.equ BOOTSZ1 = 2 ; Select Boot Size
|
||
|
|
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
|
||
|
|
.equ CKOPT = 4 ; Oscillator Options
|
||
|
|
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
||
|
|
.equ JTAGEN = 6 ; Enable JTAG
|
||
|
|
.equ OCDEN = 7 ; Enable OCD
|
||
|
|
|
||
|
|
; Data Memory
|
||
|
|
.equ FLASHEND = 0x1fff ; Note: Word address
|
||
|
|
.equ IOEND = 0x003f
|
||
|
|
.equ SRAM_START = 0x0060
|
||
|
|
.equ SRAM_SIZE = 1024
|
||
|
|
.equ RAMEND = 0x045f
|
||
|
|
.equ XRAMEND = 0x0000
|
||
|
|
.equ E2END = 0x01ff
|
||
|
|
.equ EEPROMEND = 0x01ff
|
||
|
|
.equ EEADRBITS = 9
|
||
|
|
|
||
|
|
; Bootloader
|
||
|
|
.equ NRWW_START_ADDR = 0x1c00
|
||
|
|
.equ NRWW_STOP_ADDR = 0x1fff
|
||
|
|
.equ RWW_START_ADDR = 0x0
|
||
|
|
.equ RWW_STOP_ADDR = 0x1bff
|
||
|
|
.equ PAGESIZE = 64
|
||
|
|
.equ FIRSTBOOTSTART = 0x1f80
|
||
|
|
.equ SECONDBOOTSTART = 0x1f00
|
||
|
|
.equ THIRDBOOTSTART = 0x1e00
|
||
|
|
.equ FOURTHBOOTSTART = 0x1c00
|
||
|
|
.equ SMALLBOOTSTART = FIRSTBOOTSTART
|
||
|
|
.equ LARGEBOOTSTART = FOURTHBOOTSTART
|
||
|
|
|
||
|
|
; Interrupt Vectors
|
||
|
|
.equ INT0addr = 0x0002 ; External Interrupt Request 0
|
||
|
|
.equ INT1addr = 0x0004 ; External Interrupt Request 1
|
||
|
|
.equ OC2addr = 0x0006 ; Timer/Counter2 Compare Match
|
||
|
|
.equ OVF2addr = 0x0008 ; Timer/Counter2 Overflow
|
||
|
|
.equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event
|
||
|
|
.equ OC1Aaddr = 0x000c ; Timer/Counter1 Compare Match A
|
||
|
|
.equ OC1Baddr = 0x000e ; Timer/Counter1 Compare Match B
|
||
|
|
.equ OVF1addr = 0x0010 ; Timer/Counter1 Overflow
|
||
|
|
.equ OVF0addr = 0x0012 ; Timer/Counter0 Overflow
|
||
|
|
.equ SPIaddr = 0x0014 ; Serial Transfer Complete
|
||
|
|
.equ URXCaddr = 0x0016 ; USART, Rx Complete
|
||
|
|
.equ UDREaddr = 0x0018 ; USART Data Register Empty
|
||
|
|
.equ UTXCaddr = 0x001a ; USART, Tx Complete
|
||
|
|
.equ ADCCaddr = 0x001c ; ADC Conversion Complete
|
||
|
|
.equ ERDYaddr = 0x001e ; EEPROM Ready
|
||
|
|
.equ ACIaddr = 0x0020 ; Analog Comparator
|
||
|
|
.equ TWIaddr = 0x0022 ; 2-wire Serial Interface
|
||
|
|
.equ INT2addr = 0x0024 ; External Interrupt Request 2
|
||
|
|
.equ OC0addr = 0x0026 ; Timer/Counter0 Compare Match
|
||
|
|
.equ SPMRaddr = 0x0028 ; Store Program Memory Ready
|
||
|
|
|
||
|
|
.equ INT_VECTORS_SIZE = 42 ; size in words
|
||
|
|
|