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<h1>20161031 - FPGA Links</h1>
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<a href="http://fpgacpu.ca/fpga/priority.html">Better Priority Arbiter</a><br>
<a href="http://fpgacpu.ca/multiport/TRETS2014-LaForest-Article.pdf">Composing Multi-Ported Memories on FPGAs</a><br>
<a href="http://fpgacpu.ca/">FPGACPU.ca</a><br>
<a href="http://www.ece.ubc.ca/~stevew/papers/pdf/imran_masc.pdf">FPGA Routing Structures: A Novel Switch Block and Depopulated Interconnect Matrix Architectures</a><br>
<a href="http://fpgacpu.ca/octavo/High-Speed_Soft-Processor_Architecture_for_FPGA_Overlays.pdf">High-Speed Soft-Processor Architecture for FPGA Overlays</a><br>
<a href="http://opencores.org/project,hive">Hive - 32 bit, 8 thread, 4 register/stack hybrid, pipelined verilog soft processor core</a><br>
<a href="http://www.ece.ubc.ca/~lemieux/publications/abdelhadi-fpga2014.pdf">Modular Multi-ported SRAM-based Memories</a><br>
<a href="http://www.spartanmc.de/">SpartanMC - An FPGA soft core with an 18-bit word size, with a SPARC like sliding register window</a><br>
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