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91 lines
3.6 KiB
HTML
91 lines
3.6 KiB
HTML
<html><head><link rel="stylesheet" href="style.css"></head><body><div class="page">
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<h1>20161022 - Variation on Branching Design - Return Only</h1>
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<br>
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<i>Thoughts related to <a href="20161016.html">Instruction Fetch Optimization</a>, a post which talked about only auto-incrementing the lower 8-bits of the program counter, having even-only branch addresses to remove an ADDer delay...</i><br>
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<br>
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<b>Return Only ISA</b>
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<br>
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The point here is to be able to know the next program counter, even with a branch, a clock cycle ahead to remove instruction fetch latency from a larger RAM.
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This works with absolute branching (no relative branching).
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The minimal ISA has the following,
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<br>
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<br>
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(1.) Push immediate absolute address on return stack.<br>
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(2.) Push computed absolute address from register on return stack.<br>
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(3.) 1-bit flag in ISA (on all instructions) to return after 1 cycle delay.
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<br>
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<br>
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So the return bit causes the top of the return stack to be registered for fetch.
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Assume an optimization here where a push immediate with a return gets transformed into just setting that registered value.
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Bunch of usage cases,
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<br>
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<br>
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<pre>// RETURN
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opcode, ret; // ... register for future return
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opcode; // ........ branch delay slot
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// ................ actual return
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// COMPUTED JUMP
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push reg, ret; // ... push jump address from register and register for future return
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opcode; // .......... branch delay slot
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// .................. actual jump
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// JUMP
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push imm, ret; // ... push jump address and register for future return
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opcode; // .......... branch delay slot
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// .................. actual jump
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// CAN PUSH ADDRESS EARLIER
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push imm; // ...... push jump address to later branch to
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opcode; // ........ some code
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opcode; // ........ some code
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opcode, ret; // ... register for future return
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opcode; // ........ branch delay slot
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// ................ actual jump
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// SERIES OF JUMPS
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push imm; // ........ push addresses for series of branches in reverse order
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push imm; // ........ push addresses for series of branches in reverse order
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push imm, ret; // ... push first jump address and register for future return
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opcode; // .......... branch delay slot
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// .................. start first jump, later rets continue to other jumps
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// SERIES OF JUMPS VERSION 2
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push imm; // ........ push 4th jump address
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push imm; // ........ push 3rd jump address
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push imm, ret; // ... push 1st jump address and register for future return
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push imm; // ........ push 2nd jump in branch delay slot
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// .................. start first jump, later rets continue to other jumps
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// CALL
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push imm, ret; // ... push call address and register for future return
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push imm; // ........ push return address in delay slot
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// .................. actual call here
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// SERIES OF CALLS
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push imm; // ........ push 3nd call address
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push imm; // ........ push 2nd call address
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push imm, ret; // ... push 1st call address and flag for future return
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push imm; // ........ push final call return address in delay slot
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// .................. start first call, later rets continue without returning back in between</pre>
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<br>
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No need for call/jump right after logical return (which would have a delay slot), because that can always be factored to a "series" case.
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<br>
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<br>
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Another option would be a co-return bit in addition to the return bit.
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The co-return would swap the top of the return stack with the program counter + 1.
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This would remove the need to push the final return address for a single call,
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but won't help with a series of calls (cannot use the co-return, as need reverse order).
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<br>
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</div></body></html>
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