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45 lines
1.9 KiB
HTML
45 lines
1.9 KiB
HTML
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<h1>20161015 - Atomic Scatter-Only Gather-Free Machines</h1>
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GPUs are build around having texture caches,
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and caches are build around collecting loads for the most part,
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because loads have the highest memory traffic typically.
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So if after stripping out the caches from a highly parallel machine,
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perhaps gathering data to centralized location for processing,
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and then scattering it out again, is not the best model?
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One possible alternative would be to switch to a scatter-centric design.
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On-chip memory gets divided across all the cores.
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Each core contains the required remote procedure (RP) functions to interact with the data associated with the core.
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Programs are composed of fire-and-forget message passing.
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Message contains arguments to the RP and index/address of the RP to execute.
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The model is return-free,
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and the RP only has access to the arguments in the message and the local memory of the core.
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This is conceptually similar to taking the GPU's global atomic without return, and making it fully programmable.
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This brings up a new challenge,
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that in order to fully load the machine,
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data needs to be evenly distributed across the cores based on amount of RP access.
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Conceptually in this model, each core is a bank of distributed memory, and a mid-range FPGA might have upwards of 1024 banks (each one BRAM).
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Need to ensure an algorithm doesn't camp on one bank of memory.
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Likewise if any data is duplicated across cores for the sake of higher throughput,
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one might want to build in something into the routing logic which takes the first found compatible core which can service the RP.
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Also message broadcast with variable 2D locality would be very important for data amplification.
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