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61 lines
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HTML
61 lines
2.3 KiB
HTML
<html><head><link rel="stylesheet" href="style.css"></head><body><div class="page">
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<h1>20160705 - CPU Threading to Hide Pipelining</h1>
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<br>
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If a CPU has a 4 stage pipeline, would be nice to have 4 CPU threads round robin scheduled to ensure pipeline delays for {memory, alu, branches, etc} do not have to be programmer visible,
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and to avoid complexities such as forwarding.
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<br>
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<br>
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According to docs,
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Xilinx 7-series <a href="http://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf">DSPs</a> need a 3 stage pipeline for full speed MAC,
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and <a href="www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf">BRAMs (Block RAMs)</a> need 1 cycle delay for reads.
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<br>
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<br>
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Working from high level constraints, I'm planning using the following for the CPU-side of the project,
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<br>
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<br><tt>
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16-bit or 18-bit machine<br>
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1 DSP<br>
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X BRAMs of Instruction RAM (2 ports, read or write for either)<br>
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Y BRAMs of Data RAM (2 ports, read or write for either)
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</tt><br>
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<br>
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Which suggests the following 4 stage pipeline (with 4 CPU threads running in parallel, one on each pipeline stage),
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<br>
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<br><tt>
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[0]<br>
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Instruction BRAM Read -> Instruction BRAM Registers<br>
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DSP MUL -> DSP {M,C} Registers (from prior instruction)<br>
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<br>
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[1]<br>
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Instruction Decode<br>
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DSP ALU -> DSP {P} Registers (from prior instruction)<br>
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<br>
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[2]<br>
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Data BRAM Write(s) (results from prior instruction)<br>
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Data BRAM Read(s) -> Data BRAM Registers<br>
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<br>
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[3]<br>
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DSP Input -> DSP {A,B,D} Registers
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</tt><br>
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<br>
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With an ISA which can do something as complex as the following (below) in one instruction.
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A focus on instruction forms which can leverage both ports on the Instruction BRAMs (opcode and separate optional immediate),
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as well as both ports on the Data BRAMs.
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Using dedicated address registers to provide windows into the Data BRAMs for immediate access instead of a conventional register file,
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and leveraging a special high-bit-width accumulator to maintain precision of intermediate fixed-point operations.
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<br>
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<br><tt>
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[addressRegister[2bitImmediate]^nbitImmediate] = accumulator;<br>
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accumulator = [addressRegister[2bitImmediate]^nbitImmediate]] OP 18bitImmediate;
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</tt><br>
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</div></body></html>
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