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27 lines
1.2 KiB
HTML
27 lines
1.2 KiB
HTML
<html><head><link rel="stylesheet" href="style.css"></head><body><div class="page">
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<h1>20150911 - Self-Correcting CPU Pipelines</h1>
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<br>
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<i>Elaborating an idea which came up in a prior conversation...</i><br>
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<br>
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The aim is to make CPU programming as fun and easy as iterative run-time edit reload based GPU shader programming.
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Re-purpose the CPU page tables for intra-app memory protection between in-app tasks.
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Effectively providing hardware protection for functional programming.
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When in-app tasks switch, adjust page table protection, then use INVLPG (on 486 and up) to flush TLB entries for changed pages.
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The page tables change to disallow writes to now read-only data from the prior completed job,
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and to allow writes to write-able data for the current job.
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Use x86's support for various page sizes and pre-staged page tables for fixed jobs to make this efficient.
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Setup a background watchdog to act as a TDR check, to reset to a stable state if any task runs too long (infinite loop, etc).
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The "kernels" or CPU jobs which transform data can also be designed to be somewhat self correcting,
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using min or max to limit indexes, etc...
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</div></body></html>
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