mirror of
https://github.com/Ed94/Odin.git
synced 2026-06-14 09:52:23 -07:00
Barinzaya
9d40f371be
This uses compile-time features to decide how large of a SIMD vector to use. It currently has checks for amd64/i386 to size its vectors for SSE2/AVX2/AVX512 as necessary. The generalized SIMD functions could also be useful for multiversioning of the hash procs, to allow for run-time dispatch based on available CPU features.
136 lines
3.5 KiB
Odin
136 lines
3.5 KiB
Odin
/*
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Copyright 2021 Jeroen van Rijn <nom@duclavier.com>.
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Made available under Odin's BSD-3 license, based on the original C code.
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List of contributors:
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Jeroen van Rijn: Initial implementation.
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*/
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// An implementation of Yann Collet's [[ xxhash Fast Hash Algorithm; https://cyan4973.github.io/xxHash/ ]].
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package xxhash
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import "base:intrinsics"
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import "base:runtime"
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mem_copy :: runtime.mem_copy
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byte_swap :: intrinsics.byte_swap
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/*
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Version definition
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*/
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XXH_VERSION_MAJOR :: 0
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XXH_VERSION_MINOR :: 8
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XXH_VERSION_RELEASE :: 1
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XXH_VERSION_NUMBER :: XXH_VERSION_MAJOR * 100 * 100 + XXH_VERSION_MINOR * 100 + XXH_VERSION_RELEASE
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/*
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0 - Use memcopy, for platforms where unaligned reads are a problem
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2 - Direct cast, for platforms where unaligned are allowed (default)
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*/
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XXH_FORCE_MEMORY_ACCESS :: #config(XXH_FORCE_MEMORY_ACCESS, 2)
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/*
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`false` - Use this on platforms where unaligned reads are fast
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`true` - Use this on platforms where unaligned reads are slow
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*/
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XXH_FORCE_ALIGN_CHECK :: #config(XXH_FORCE_ALIGN_CHECK, false)
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Alignment :: enum {
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Aligned,
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Unaligned,
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}
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Error :: enum {
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None = 0,
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Error,
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}
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XXH_DISABLE_PREFETCH :: #config(XXH_DISABLE_PREFETCH, true)
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/*
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llvm.prefetch fails code generation on Linux.
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*/
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when !XXH_DISABLE_PREFETCH {
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prefetch_address :: #force_inline proc(address: rawptr) {
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intrinsics.prefetch_read_data(address, /*high*/3)
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}
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prefetch_offset :: #force_inline proc(address: rawptr, #any_int offset: uintptr) {
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ptr := rawptr(uintptr(address) + offset)
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prefetch_address(ptr)
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}
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prefetch :: proc { prefetch_address, prefetch_offset, }
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} else {
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prefetch_address :: #force_inline proc(address: rawptr) {
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}
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prefetch_offset :: #force_inline proc(address: rawptr, #any_int offset: uintptr) {
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}
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}
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@(optimization_mode="favor_size")
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XXH_rotl32 :: #force_inline proc(x, r: u32) -> (res: u32) {
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return ((x << r) | (x >> (32 - r)))
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}
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@(optimization_mode="favor_size")
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XXH_rotl64 :: #force_inline proc(x, r: u64) -> (res: u64) {
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return ((x << r) | (x >> (64 - r)))
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}
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@(optimization_mode="favor_size")
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XXH32_read32 :: #force_inline proc(buf: []u8, alignment := Alignment.Unaligned) -> (res: u32) {
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if XXH_FORCE_MEMORY_ACCESS == 2 || alignment == .Aligned {
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#no_bounds_check b := (^u32le)(&buf[0])^
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return u32(b)
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} else {
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b: u32le
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mem_copy(&b, raw_data(buf[:]), 4)
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return u32(b)
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}
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}
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@(optimization_mode="favor_size")
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XXH64_read64 :: #force_inline proc(buf: []u8, alignment := Alignment.Unaligned) -> (res: u64) {
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if XXH_FORCE_MEMORY_ACCESS == 2 || alignment == .Aligned {
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#no_bounds_check b := (^u64le)(&buf[0])^
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return u64(b)
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} else {
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b: u64le
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mem_copy(&b, raw_data(buf[:]), 8)
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return u64(b)
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}
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}
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XXH64_read64_simd :: #force_inline proc(buf: []$E, $W: uint, alignment := Alignment.Unaligned) -> (res: #simd[W]u64) {
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if alignment == .Aligned {
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res = (^#simd[W]u64)(raw_data(buf))^
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} else {
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res = intrinsics.unaligned_load((^#simd[W]u64)(raw_data(buf)))
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}
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when ODIN_ENDIAN == .Big {
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bytes := transmute(#simd[W*8]u8)res
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bytes = intrinsics.simd_lanes_reverse(bytes)
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res = transmute(#simd[W]u64)bytes
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res = intrinsics.simd_lanes_reverse(res)
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}
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return
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}
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XXH64_write64_simd :: #force_inline proc(buf: []$E, value: $V/#simd[$W]u64, alignment := Alignment.Unaligned) {
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value := value
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when ODIN_ENDIAN == .Big {
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bytes := transmute(#simd[W*8]u8)value
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bytes = intrinsics.simd_lanes_reverse(bytes)
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value = transmute(#simd[W]u64)bytes
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value = intrinsics.simd_lanes_reverse(value)
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}
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if alignment == .Aligned {
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(^V)(raw_data(buf))^ = value
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} else {
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intrinsics.unaligned_store((^V)(raw_data(buf)), value)
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}
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}
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