6ebd30033f
Removed an extra character that slipped into a comment.
2025-05-03 13:24:22 -04:00
8b6436201e
Fixed a reduce_add proc doing multiplication instead.
2025-05-03 13:04:11 -04:00
7e34d707bb
core:simd helpers: indices and reduce_add/mul
...
The indices proc simply creates a vector where each lane contains its
own lane index. This can be useful for use in generating masks for loads
and stores at the beginning/end of slices, among other things.
The new reduce_add/reduce_mul procs perform the corresponding arithmetic
reduction, in different orders than just "in sequential order". These
alternative orders can often be faster to calculate, as they can offer
better SIMD hardware utilization.
Two different orders are added for these: pair-wise (operating on
adjacent pairs of elements) or split-wise (operating element-wise on the
two halves of the vector).
This doesn't actually cover the *fastest* way for arbitrarily-sized
vectors. That would be an ordered reduction across the native vector
width, then reducing the resulting vector to a scalar in an appropriate
parallel fashion. I'd created an implementation of that, but it required
multiple procs and a fair bit more trickery than I was comfortable with
submitting to `core`, so it's not included yet. Maybe in the future.
2025-05-03 11:55:52 -04:00
f7c4c80ef3
Fix broken examples in documentation tester.
...
No more:
```
We could not find the procedure "pkg_foo_example :: proc()" needed to test the example created for "pkg.foo"
The following procedures were found:
bar()
```
2025-04-05 16:36:26 +02:00
70daf40cb1
Fix documentation for simd_shuffle
2025-03-02 20:42:13 +11:00
698c510ba7
Merge branch 'master' into docs-simd
2025-03-02 20:05:55 +11:00
4afedbc051
Added simd_extract_lsbs intrinsic as well.
...
Equivalent to the simd_extract_msbs intrinsic, except it extracts the
least significant bit of each element instead.
2025-02-24 08:49:57 -05:00
33a3aab791
Added simd_extract_msbs intrinsic.
2025-02-24 08:39:32 -05:00
5d290dce06
Merge branch 'simd-docs' into docs-simd
2025-01-21 11:45:51 +11:00
b7afbd6d57
Suggestion fixes
2025-01-21 11:15:00 +11:00
dfe3073cef
[simd] Fixes to inputs/result/example/output sections & grmamar fixes
2025-01-08 16:47:12 +03:00
49b8abe3ef
Apply suggestions from code review
...
Co-authored-by: Laytan <laytanlaats@hotmail.com >
2024-12-04 22:50:10 +11:00
ba6224b61a
Apply suggestions from code review
...
Co-authored-by: Laytan <laytanlaats@hotmail.com >
2024-12-04 19:11:21 +11:00
8387561d0a
[core/simd]: Write package documentation
2024-12-02 01:24:33 +11:00
d41c7d52e7
Fix indentation
2024-12-01 11:50:00 +11:00
d48c351330
Fix indentation
2024-12-01 11:48:52 +11:00
596921fb7a
First pass
2024-12-01 11:42:24 +11:00
58e5078b66
add riscv to simd.IS_EMULATED
2024-08-22 14:17:45 +02:00
7020e9b66a
core/simd: Add IS_EMULTATED so there is one place to look for potatos
2024-08-18 22:52:39 +09:00
f56abf3780
Add intrinsics.masked_expand_load and intrinsics.masked_compress_store
2024-08-05 14:54:09 +01:00
78919f8524
Fix typos
2024-08-05 14:48:55 +01:00
84ac56f778
Add intrinsics.simd_masked_load and intrinsics.simd_masked_store
2024-08-05 14:08:41 +01:00
7e701d1677
Add intrinsics.simd_gather and `intrinsics.simd_scatter
2024-08-05 13:46:24 +01:00
90fc52c2ee
Rename add_sat -> saturating_add
2024-08-05 13:19:01 +01:00
9a01a13914
Add simd_reduce_any and simd_reduce_all
2024-08-05 13:13:19 +01:00
3e7e779abf
Replace core:* to base:* where appropriate
2024-01-28 22:18:51 +00:00
63f755554b
Rename simd bitwise operations from intrinsics.simd_and to intrinsics.simd_bit_and etc
2023-09-28 16:42:08 +01:00
bb7f291f5f
Remove simd_rem; Disallow simd_div for integers
2022-06-02 12:10:43 +01:00
cef022539e
Rename to lanes_rotate_left, lanes_rotate_right, lanes_reverse
2022-05-29 15:13:14 +01:00
952f294bce
Add loads of aliases of vector types
2022-05-27 12:20:48 +01:00
1ff8b97dae
Add prefix of lanes_
2022-05-26 20:44:37 +01:00
70451f9335
Support reverse_bits for #simd
2022-05-26 20:40:48 +01:00
1f438d4e6c
Merge intrinsics.simd_sqrt with intrinsics.sqrt
2022-05-26 18:09:59 +01:00
421d45a7a7
Add intrinsics.fused_mul_add
2022-05-26 18:06:26 +01:00
20e7b5c88a
Support count_ones etc with #simd
2022-05-26 17:48:51 +01:00
7092273a8f
Rename simd_eq etc to simd_lanes_eq
2022-05-26 17:36:13 +01:00
d0e8a735ba
Add arithmetic operator support for simd vectors; Add intrinsics.simd_and_not
2022-05-26 17:09:46 +01:00
f308f37ba1
Remove need for simd.splat
2022-05-26 14:51:50 +01:00
c2610cb75e
Keep -vet happy
2022-05-26 13:56:35 +01:00
59e9df2609
simd.bit_not; simd.copysign
2022-05-26 13:49:27 +01:00
f3f6c12a7c
Add simd_clamp
2022-05-26 11:58:55 +01:00
e331b0647e
Add simd_rotate_left simd_rotate_right`
2022-05-26 11:48:04 +01:00
35502816c7
Add simd_add_sat simd_sub_sat
2022-05-26 11:24:10 +01:00
7ec0236fbf
Add simd_reverse
2022-05-26 11:14:22 +01:00
0fd43c1a0b
Add simd.{sqrt, ceil, floor, trunc, nearest}
2022-05-26 11:02:02 +01:00
cde6a2f7a5
Make simd_shuffle act closer to swizzle
2022-05-26 00:36:24 +01:00
c2f5cbdeb4
Allow integer vectors in select
2022-05-25 23:49:23 +01:00
8e57511ffa
Minor clean up
2022-05-25 23:42:25 +01:00
12d19d21c4
Document simd stuff in intrinsics.odin
2022-05-25 23:40:59 +01:00
7002c94a63
Add intrinsics.simd_select
2022-05-25 23:34:41 +01:00
Barinzaya
Jeroen van Rijn
flysand7
flysand7
Laytan Laats
Yawning Angel
gingerBill