ed/Odin
1
0
Fork 0
mirror of https://github.com/Ed94/Odin.git synced 2026-08-01 20:28:15 +00:00
Code Issues Packages Projects Releases Wiki Activity

amd64 support half in the abi too

Browse Source
This commit is contained in:
Laytan
2025-07-31 20:50:46 +02:00
parent c3bae964d0
commit f32ee28e6d
1 changed files with 21 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/llvm_abi.cpp
+21 -2
View File
@@ -527,6 +527,8 @@ namespace lbAbiAmd64SysV {
enum RegClass { enum RegClass {
RegClass_NoClass, RegClass_NoClass,
RegClass_Int, RegClass_Int,
RegClass_SSEHs,
RegClass_SSEHv,
RegClass_SSEFs, RegClass_SSEFs,
RegClass_SSEFv, RegClass_SSEFv,
RegClass_SSEDs, RegClass_SSEDs,
@@ -545,6 +547,8 @@ namespace lbAbiAmd64SysV {
gb_internal bool is_sse(RegClass reg_class) { gb_internal bool is_sse(RegClass reg_class) {
switch (reg_class) { switch (reg_class) {
case RegClass_SSEHs:
case RegClass_SSEHv:
case RegClass_SSEFs: case RegClass_SSEFs:
case RegClass_SSEFv: case RegClass_SSEFv:
case RegClass_SSEDs: case RegClass_SSEDs:
@@ -693,6 +697,8 @@ namespace lbAbiAmd64SysV {
case RegClass_Int: case RegClass_Int:
needed_int += 1; needed_int += 1;
break; break;
case RegClass_SSEHs:
case RegClass_SSEHv:
case RegClass_SSEFs: case RegClass_SSEFs:
case RegClass_SSEFv: case RegClass_SSEFv:
case RegClass_SSEDs: case RegClass_SSEDs:
@@ -804,6 +810,8 @@ namespace lbAbiAmd64SysV {
to_write = RegClass_Memory; to_write = RegClass_Memory;
} else if (newv == RegClass_SSEUp) { } else if (newv == RegClass_SSEUp) {
switch (oldv) { switch (oldv) {
case RegClass_SSEHv:
case RegClass_SSEHs:
case RegClass_SSEFv: case RegClass_SSEFv:
case RegClass_SSEFs: case RegClass_SSEFs:
case RegClass_SSEDv: case RegClass_SSEDv:
@@ -918,6 +926,7 @@ namespace lbAbiAmd64SysV {
sz -= rs; sz -= rs;
break; break;
} }
case RegClass_SSEHv:
case RegClass_SSEFv: case RegClass_SSEFv:
case RegClass_SSEDv: case RegClass_SSEDv:
case RegClass_SSEInt8: case RegClass_SSEInt8:
@@ -928,6 +937,10 @@ namespace lbAbiAmd64SysV {
unsigned elems_per_word = 0; unsigned elems_per_word = 0;
LLVMTypeRef elem_type = nullptr; LLVMTypeRef elem_type = nullptr;
switch (reg_class) { switch (reg_class) {
case RegClass_SSEHv:
elems_per_word = 4;
elem_type = LLVMHalfTypeInContext(c);
break;
case RegClass_SSEFv: case RegClass_SSEFv:
elems_per_word = 2; elems_per_word = 2;
elem_type = LLVMFloatTypeInContext(c); elem_type = LLVMFloatTypeInContext(c);
@@ -962,6 +975,10 @@ namespace lbAbiAmd64SysV {
continue; continue;
} }
break; break;
case RegClass_SSEHs:
array_add(&types, LLVMHalfTypeInContext(c));
sz -= 2;
break;
case RegClass_SSEFs: case RegClass_SSEFs:
array_add(&types, LLVMFloatTypeInContext(c)); array_add(&types, LLVMFloatTypeInContext(c));
sz -= 4; sz -= 4;
@@ -1008,9 +1025,11 @@ namespace lbAbiAmd64SysV {
break; break;
} }
case LLVMPointerTypeKind: case LLVMPointerTypeKind:
case LLVMHalfTypeKind:
unify(cls, ix + off/8, RegClass_Int); unify(cls, ix + off/8, RegClass_Int);
break; break;
case LLVMHalfTypeKind:
unify(cls, ix + off/8, (off%8 == 2) ? RegClass_SSEHv : RegClass_SSEHs);
break;
case LLVMFloatTypeKind: case LLVMFloatTypeKind:
unify(cls, ix + off/8, (off%8 == 4) ? RegClass_SSEFv : RegClass_SSEFs); unify(cls, ix + off/8, (off%8 == 4) ? RegClass_SSEFv : RegClass_SSEFs);
break; break;
@@ -1070,7 +1089,7 @@ namespace lbAbiAmd64SysV {
break; break;
}; };
case LLVMHalfTypeKind: case LLVMHalfTypeKind:
reg = RegClass_SSEInt16; reg = RegClass_SSEHv;
break; break;
case LLVMFloatTypeKind: case LLVMFloatTypeKind:
reg = RegClass_SSEFv; reg = RegClass_SSEFv;