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amd64 abi fixes regarding vectors

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- Fixes the code so SSEUp is grouped/skipped over properly (Fixes #5429)
- Fixes f16 vectors using garbage widths, because it would call
LLVMGetIntTypeWidth and an f16 is not an int so doesn't have that
function
This commit is contained in:
Laytan
2025-07-31 20:26:22 +02:00
parent 939fed592d
commit c3bae964d0
1 changed files with 16 additions and 9 deletions
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src/llvm_abi.cpp
+16 -9
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@@ -850,14 +850,18 @@ namespace lbAbiAmd64SysV {
} else if (oldv == RegClass_SSEUp) { } else if (oldv == RegClass_SSEUp) {
oldv = RegClass_SSEDv; oldv = RegClass_SSEDv;
} else if (is_sse(oldv)) { } else if (is_sse(oldv)) {
i++; for (i++; i < e; i++) {
while (i != e && oldv == RegClass_SSEUp) { RegClass v = (*cls)[cast(isize)i];
i++; if (v != RegClass_SSEUp) {
break;
}
} }
} else if (oldv == RegClass_X87) { } else if (oldv == RegClass_X87) {
i++; for (i++; i < e; i++) {
while (i != e && oldv == RegClass_X87Up) { RegClass v = (*cls)[cast(isize)i];
i++; if (v != RegClass_X87Up) {
break;
}
} }
} else { } else {
i++; i++;
@@ -1046,10 +1050,9 @@ namespace lbAbiAmd64SysV {
i64 elem_sz = lb_sizeof(elem); i64 elem_sz = lb_sizeof(elem);
LLVMTypeKind elem_kind = LLVMGetTypeKind(elem); LLVMTypeKind elem_kind = LLVMGetTypeKind(elem);
RegClass reg = RegClass_NoClass; RegClass reg = RegClass_NoClass;
unsigned elem_width = LLVMGetIntTypeWidth(elem);
switch (elem_kind) { switch (elem_kind) {
case LLVMIntegerTypeKind: case LLVMIntegerTypeKind: {
case LLVMHalfTypeKind: unsigned elem_width = LLVMGetIntTypeWidth(elem);
switch (elem_width) { switch (elem_width) {
case 8: reg = RegClass_SSEInt8; break; case 8: reg = RegClass_SSEInt8; break;
case 16: reg = RegClass_SSEInt16; break; case 16: reg = RegClass_SSEInt16; break;
@@ -1065,6 +1068,10 @@ namespace lbAbiAmd64SysV {
GB_PANIC("Unhandled integer width for vector type %u", elem_width); GB_PANIC("Unhandled integer width for vector type %u", elem_width);
} }
break; break;
};
case LLVMHalfTypeKind:
reg = RegClass_SSEInt16;
break;
case LLVMFloatTypeKind: case LLVMFloatTypeKind:
reg = RegClass_SSEFv; reg = RegClass_SSEFv;
break; break;